cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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mediatek,mt7621-gpio.yaml (1580B)

      1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/gpio/mediatek,mt7621-gpio.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Mediatek MT7621 SoC GPIO controller
      8
      9maintainers:
     10  - Sergio Paracuellos <sergio.paracuellos@gmail.com>
     11
     12description: |
     13  The IP core used inside these SoCs has 3 banks of 32 GPIOs each.
     14  The registers of all the banks are interwoven inside one single IO range.
     15  We load one GPIO controller instance per bank. Also the GPIO controller can receive
     16  interrupts on any of the GPIOs, either edge or level. It then interrupts the CPU
     17  using GIC INT12.
     18
     19properties:
     20  $nodename:
     21    pattern: "^gpio@[0-9a-f]+$"
     22
     23  compatible:
     24    const: mediatek,mt7621-gpio
     25
     26  reg:
     27    maxItems: 1
     28
     29  "#gpio-cells":
     30    const: 2
     31
     32  gpio-controller: true
     33  gpio-ranges: true
     34
     35  interrupt-controller: true
     36
     37  "#interrupt-cells":
     38    const: 2
     39
     40  interrupts:
     41    maxItems: 1
     42
     43required:
     44  - compatible
     45  - reg
     46  - "#gpio-cells"
     47  - gpio-controller
     48  - gpio-ranges
     49  - interrupt-controller
     50  - "#interrupt-cells"
     51  - interrupts
     52
     53additionalProperties: false
     54
     55examples:
     56  - |
     57    #include <dt-bindings/gpio/gpio.h>
     58    #include <dt-bindings/interrupt-controller/mips-gic.h>
     59
     60    gpio@600 {
     61      compatible = "mediatek,mt7621-gpio";
     62      reg = <0x600 0x100>;
     63      #gpio-cells = <2>;
     64      gpio-controller;
     65      gpio-ranges = <&pinctrl 0 0 95>;
     66      interrupt-controller;
     67      #interrupt-cells = <2>;
     68      interrupt-parent = <&gic>;
     69      interrupts = <GIC_SHARED 12 IRQ_TYPE_LEVEL_HIGH>;
     70    };
     71
     72...