cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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microchip,pic32-gpio.txt (1457B)

      1* Microchip PIC32 GPIO devices (PIO).
      2
      3Required properties:
      4 - compatible: "microchip,pic32mzda-gpio"
      5 - reg: Base address and length for the device.
      6 - interrupts: The port interrupt shared by all pins.
      7 - gpio-controller: Marks the port as GPIO controller.
      8 - #gpio-cells: Two. The first cell is the pin number and
      9   the second cell is used to specify the gpio polarity as defined in
     10   defined in <dt-bindings/gpio/gpio.h>:
     11      0 = GPIO_ACTIVE_HIGH
     12      1 = GPIO_ACTIVE_LOW
     13      2 = GPIO_OPEN_DRAIN
     14 - interrupt-controller: Marks the device node as an interrupt controller.
     15 - #interrupt-cells: Two. The first cell is the GPIO number and second cell
     16   is used to specify the trigger type as defined in
     17   <dt-bindings/interrupt-controller/irq.h>:
     18      IRQ_TYPE_EDGE_RISING
     19      IRQ_TYPE_EDGE_FALLING
     20      IRQ_TYPE_EDGE_BOTH
     21 - clocks: Clock specifier (see clock bindings for details).
     22 - microchip,gpio-bank: Specifies which bank a controller owns.
     23 - gpio-ranges: Interaction with the PINCTRL subsystem.
     24
     25Example:
     26
     27/* PORTA */
     28gpio0: gpio0@1f860000 {
     29	compatible = "microchip,pic32mzda-gpio";
     30	reg = <0x1f860000 0x100>;
     31	interrupts = <118 IRQ_TYPE_LEVEL_HIGH>;
     32	#gpio-cells = <2>;
     33	gpio-controller;
     34	interrupt-controller;
     35	#interrupt-cells = <2>;
     36	clocks = <&rootclk PB4CLK>;
     37	microchip,gpio-bank = <0>;
     38	gpio-ranges = <&pic32_pinctrl 0 0 16>;
     39};
     40
     41keys {
     42	...
     43
     44	button@sw1 {
     45		label = "ESC";
     46		linux,code = <1>;
     47		gpios = <&gpio0 12 0>;
     48	};
     49};