cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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rockchip,gpio-bank.yaml (1690B)

      1# SPDX-License-Identifier: GPL-2.0
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/gpio/rockchip,gpio-bank.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Rockchip GPIO bank
      8
      9maintainers:
     10  - Heiko Stuebner <heiko@sntech.de>
     11
     12properties:
     13  compatible:
     14    enum:
     15      - rockchip,gpio-bank
     16      - rockchip,rk3188-gpio-bank0
     17
     18  reg:
     19    maxItems: 1
     20
     21  interrupts:
     22    maxItems: 1
     23
     24  clocks:
     25    minItems: 1
     26    items:
     27      - description: APB interface clock source
     28      - description: GPIO debounce reference clock source
     29
     30  gpio-controller: true
     31
     32  gpio-line-names: true
     33
     34  "#gpio-cells":
     35    const: 2
     36
     37  interrupt-controller: true
     38
     39  "#interrupt-cells":
     40    const: 2
     41
     42required:
     43  - compatible
     44  - reg
     45  - interrupts
     46  - clocks
     47  - gpio-controller
     48  - "#gpio-cells"
     49  - interrupt-controller
     50  - "#interrupt-cells"
     51
     52additionalProperties: false
     53
     54examples:
     55  - |
     56    #include <dt-bindings/interrupt-controller/arm-gic.h>
     57    pinctrl: pinctrl {
     58      #address-cells = <1>;
     59      #size-cells = <1>;
     60      ranges;
     61
     62      gpio0: gpio@2000a000 {
     63        compatible = "rockchip,rk3188-gpio-bank0";
     64        reg = <0x2000a000 0x100>;
     65        interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
     66        clocks = <&clk_gates8 9>;
     67
     68        gpio-controller;
     69        #gpio-cells = <2>;
     70
     71        interrupt-controller;
     72        #interrupt-cells = <2>;
     73      };
     74
     75      gpio1: gpio@2003c000 {
     76        compatible = "rockchip,gpio-bank";
     77        reg = <0x2003c000 0x100>;
     78        interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
     79        clocks = <&clk_gates8 10>;
     80
     81        gpio-controller;
     82        #gpio-cells = <2>;
     83
     84        interrupt-controller;
     85        #interrupt-cells = <2>;
     86      };
     87    };