cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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socionext,uniphier-gpio.yaml (2803B)

      1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/gpio/socionext,uniphier-gpio.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: UniPhier GPIO controller
      8
      9maintainers:
     10  - Masahiro Yamada <yamada.masahiro@socionext.com>
     11
     12properties:
     13  $nodename:
     14    pattern: "^gpio@[0-9a-f]+$"
     15
     16  compatible:
     17    const: socionext,uniphier-gpio
     18
     19  reg:
     20    maxItems: 1
     21
     22  gpio-controller: true
     23
     24  "#gpio-cells":
     25    const: 2
     26
     27  interrupt-controller: true
     28
     29  "#interrupt-cells":
     30    description: |
     31      The first cell defines the interrupt number.
     32      The second cell bits[3:0] is used to specify trigger type as follows:
     33        1 = low-to-high edge triggered
     34        2 = high-to-low edge triggered
     35        4 = active high level-sensitive
     36        8 = active low level-sensitive
     37      Valid combinations are 1, 2, 3, 4, 8.
     38    const: 2
     39
     40  ngpios:
     41    minimum: 0
     42    maximum: 512
     43
     44  gpio-ranges: true
     45
     46  gpio-ranges-group-names: true
     47
     48  socionext,interrupt-ranges:
     49    description: |
     50      Specifies an interrupt number mapping between this GPIO controller and
     51      its interrupt parent, in the form of arbitrary number of
     52      <child-interrupt-base parent-interrupt-base length> triplets.
     53    $ref: /schemas/types.yaml#/definitions/uint32-matrix
     54
     55patternProperties:
     56  "^.+-hog(-[0-9]+)?$":
     57    type: object
     58    properties:
     59      gpio-hog: true
     60      gpios: true
     61      input: true
     62      output-high: true
     63      output-low: true
     64      line-name: true
     65
     66    required:
     67      - gpio-hog
     68      - gpios
     69
     70    additionalProperties: false
     71
     72required:
     73  - compatible
     74  - reg
     75  - gpio-controller
     76  - "#gpio-cells"
     77  - interrupt-controller
     78  - "#interrupt-cells"
     79  - ngpios
     80  - gpio-ranges
     81  - socionext,interrupt-ranges
     82
     83additionalProperties: false
     84
     85examples:
     86  - |
     87    #include <dt-bindings/gpio/gpio.h>
     88    #include <dt-bindings/gpio/uniphier-gpio.h>
     89
     90    gpio: gpio@55000000 {
     91        compatible = "socionext,uniphier-gpio";
     92        reg = <0x55000000 0x200>;
     93        interrupt-parent = <&aidet>;
     94        interrupt-controller;
     95        #interrupt-cells = <2>;
     96        gpio-controller;
     97        #gpio-cells = <2>;
     98        gpio-ranges = <&pinctrl 0 0 0>;
     99        gpio-ranges-group-names = "gpio_range";
    100        ngpios = <248>;
    101        socionext,interrupt-ranges = <0 48 16>, <16 154 5>, <21 217 3>;
    102    };
    103
    104    // Consumer:
    105    // Please note UNIPHIER_GPIO_PORT(29, 4) represents PORT294 in the SoC
    106    // document. Unfortunately, only the one's place is octal in the port
    107    // numbering. (That is, PORT 8, 9, 18, 19, 28, 29, ... do not exist.)
    108    // UNIPHIER_GPIO_PORT() is a helper macro to calculate 29 * 8 + 4.
    109    sdhci0_pwrseq {
    110        compatible = "mmc-pwrseq-emmc";
    111        reset-gpios = <&gpio UNIPHIER_GPIO_PORT(29, 4) GPIO_ACTIVE_LOW>;
    112    };