cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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toshiba,gpio-visconti.yaml (1370B)

      1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/gpio/toshiba,gpio-visconti.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Toshiba Visconti ARM SoCs GPIO controller
      8
      9maintainers:
     10  - Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
     11
     12properties:
     13  compatible:
     14    items:
     15      - const: toshiba,gpio-tmpv7708
     16
     17  reg:
     18    maxItems: 1
     19
     20  "#gpio-cells":
     21    const: 2
     22
     23  gpio-ranges: true
     24
     25  gpio-controller: true
     26
     27  interrupt-controller: true
     28
     29  "#interrupt-cells":
     30    const: 2
     31
     32  interrupts:
     33    description:
     34      interrupt mapping one per GPIO.
     35    minItems: 16
     36    maxItems: 16
     37
     38required:
     39  - compatible
     40  - reg
     41  - "#gpio-cells"
     42  - gpio-ranges
     43  - gpio-controller
     44  - interrupt-controller
     45  - "#interrupt-cells"
     46
     47additionalProperties: false
     48
     49examples:
     50  - |
     51      #include <dt-bindings/interrupt-controller/irq.h>
     52      #include <dt-bindings/interrupt-controller/arm-gic.h>
     53
     54      soc {
     55        #address-cells = <2>;
     56        #size-cells = <2>;
     57
     58        gpio: gpio@28020000 {
     59          compatible = "toshiba,gpio-tmpv7708";
     60          reg = <0 0x28020000 0 0x1000>;
     61          #gpio-cells = <0x2>;
     62          gpio-ranges = <&pmux 0 0 32>;
     63          gpio-controller;
     64          interrupt-controller;
     65          #interrupt-cells = <2>;
     66          interrupt-parent = <&gic>;
     67        };
     68      };
     69...