cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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xlnx,zynqmp-gpio-modepin.yaml (918B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: "http://devicetree.org/schemas/gpio/xlnx,zynqmp-gpio-modepin.yaml#"
      5$schema: "http://devicetree.org/meta-schemas/core.yaml#"
      6
      7title: ZynqMP Mode Pin GPIO controller
      8
      9description:
     10  PS_MODE is 4-bits boot mode pins sampled on POR deassertion. Mode Pin
     11  GPIO controller with configurable from numbers of pins (from 0 to 3 per
     12  PS_MODE). Every pin can be configured as input/output.
     13
     14maintainers:
     15  - Piyush Mehta <piyush.mehta@xilinx.com>
     16
     17properties:
     18  compatible:
     19    const: xlnx,zynqmp-gpio-modepin
     20
     21  gpio-controller: true
     22
     23  "#gpio-cells":
     24    const: 2
     25
     26required:
     27  - compatible
     28  - gpio-controller
     29  - "#gpio-cells"
     30
     31additionalProperties: false
     32
     33examples:
     34  - |
     35    zynqmp-firmware {
     36        gpio {
     37            compatible = "xlnx,zynqmp-gpio-modepin";
     38            gpio-controller;
     39            #gpio-cells = <2>;
     40        };
     41    };
     42
     43...