cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

vivante,gc.yaml (1572B)

      1# SPDX-License-Identifier: GPL-2.0
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/gpu/vivante,gc.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Vivante GPU Bindings
      8
      9description: Vivante GPU core devices
     10
     11maintainers:
     12  - Lucas Stach <l.stach@pengutronix.de>
     13
     14properties:
     15  compatible:
     16    const: vivante,gc
     17
     18  reg:
     19    maxItems: 1
     20
     21  interrupts:
     22    maxItems: 1
     23
     24  '#cooling-cells':
     25    const: 2
     26
     27  assigned-clock-parents: true
     28  assigned-clock-rates: true
     29  assigned-clocks: true
     30
     31  clocks:
     32    items:
     33      - description: AXI/master interface clock
     34      - description: GPU core clock
     35      - description: Shader clock (only required if GPU has feature PIPE_3D)
     36      - description: AHB/slave interface clock (only required if GPU can gate
     37          slave interface independently)
     38    minItems: 1
     39
     40  clock-names:
     41    items:
     42      enum: [ bus, core, shader, reg ]
     43    minItems: 1
     44    maxItems: 4
     45
     46  resets:
     47    maxItems: 1
     48
     49  power-domains:
     50    maxItems: 1
     51
     52required:
     53  - compatible
     54  - reg
     55  - interrupts
     56  - clocks
     57  - clock-names
     58
     59additionalProperties: false
     60
     61examples:
     62  - |
     63    #include <dt-bindings/clock/imx6qdl-clock.h>
     64    #include <dt-bindings/interrupt-controller/arm-gic.h>
     65    gpu@130000 {
     66      compatible = "vivante,gc";
     67      reg = <0x00130000 0x4000>;
     68      interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
     69      clocks = <&clks IMX6QDL_CLK_GPU3D_AXI>,
     70               <&clks IMX6QDL_CLK_GPU3D_CORE>,
     71               <&clks IMX6QDL_CLK_GPU3D_SHADER>;
     72      clock-names = "bus", "core", "shader";
     73      power-domains = <&gpc 1>;
     74    };
     75
     76...