cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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omap-ssi.txt (2888B)

      1OMAP SSI controller bindings
      2
      3OMAP3's Synchronous Serial Interface (SSI) controller implements a
      4legacy variant of MIPI's High Speed Synchronous Serial Interface (HSI),
      5while the controller found inside OMAP4 is supposed to be fully compliant
      6with the HSI standard.
      7
      8Required properties:
      9- compatible:		Should include "ti,omap3-ssi" or "ti,omap4-hsi"
     10- reg-names:		Contains the values "sys" and "gdd" (in this order).
     11- reg:			Contains a matching register specifier for each entry
     12			in reg-names.
     13- interrupt-names:	Contains the value "gdd_mpu".
     14- interrupts: 		Contains matching interrupt information for each entry
     15			in interrupt-names.
     16- ranges:		Represents the bus address mapping between the main
     17			controller node and the child nodes below.
     18- clock-names:		Must include the following entries:
     19  "ssi_ssr_fck": The OMAP clock of that name
     20  "ssi_sst_fck": The OMAP clock of that name
     21  "ssi_ick": The OMAP clock of that name
     22- clocks:		Contains a matching clock specifier for each entry in
     23			clock-names.
     24- #address-cells:	Should be set to <1>
     25- #size-cells:		Should be set to <1>
     26
     27Each port is represented as a sub-node of the ti,omap3-ssi device.
     28
     29Required Port sub-node properties:
     30- compatible:		Should be set to the following value
     31			ti,omap3-ssi-port (applicable to OMAP34xx devices)
     32			ti,omap4-hsi-port (applicable to OMAP44xx devices)
     33- reg-names:		Contains the values "tx" and "rx" (in this order).
     34- reg:			Contains a matching register specifier for each entry
     35			in reg-names.
     36- interrupts:		Should contain interrupt specifiers for mpu interrupts
     37			0 and 1 (in this order).
     38- ti,ssi-cawake-gpio:	Defines which GPIO pin is used to signify CAWAKE
     39			events for the port. This is an optional board-specific
     40			property. If it's missing the port will not be
     41			enabled.
     42
     43Optional properties:
     44- ti,hwmods:		Shall contain TI interconnect module name if needed
     45			by the SoC
     46
     47Example for Nokia N900:
     48
     49ssi-controller@48058000 {
     50	compatible = "ti,omap3-ssi";
     51
     52	/* needed until hwmod is updated to use the compatible string */
     53	ti,hwmods = "ssi";
     54
     55	reg = <0x48058000 0x1000>,
     56	      <0x48059000 0x1000>;
     57	reg-names = "sys",
     58		    "gdd";
     59
     60	interrupts = <55>;
     61	interrupt-names = "gdd_mpu";
     62
     63	clocks = <&ssi_ssr_fck>,
     64		 <&ssi_sst_fck>,
     65		 <&ssi_ick>;
     66	clock-names = "ssi_ssr_fck",
     67		      "ssi_sst_fck",
     68		      "ssi_ick";
     69
     70	#address-cells = <1>;
     71	#size-cells = <1>;
     72	ranges;
     73
     74	ssi-port@4805a000 {
     75		compatible = "ti,omap3-ssi-port";
     76
     77		reg = <0x4805a000 0x800>,
     78		      <0x4805a800 0x800>;
     79		reg-names = "tx",
     80			    "rx";
     81
     82		interrupt-parent = <&intc>;
     83		interrupts = <67>,
     84			     <68>;
     85
     86		ti,ssi-cawake-gpio = <&gpio5 23 GPIO_ACTIVE_HIGH>; /* 151 */
     87	}
     88
     89	ssi-port@4805a000 {
     90		compatible = "ti,omap3-ssi-port";
     91
     92		reg = <0x4805b000 0x800>,
     93		      <0x4805b800 0x800>;
     94		reg-names = "tx",
     95			    "rx";
     96
     97		interrupt-parent = <&intc>;
     98		interrupts = <69>,
     99			     <70>;
    100
    101	}
    102}