cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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i2c-davinci.txt (1388B)


      1* Texas Instruments Davinci/Keystone I2C
      2
      3This file provides information, what the device node for the
      4davinci/keystone i2c interface contains.
      5
      6Required properties:
      7- compatible: "ti,davinci-i2c" or "ti,keystone-i2c";
      8- reg : Offset and length of the register set for the device
      9- clocks: I2C functional clock phandle.
     10	  For 66AK2G this property should be set per binding,
     11	  Documentation/devicetree/bindings/clock/ti,sci-clk.yaml
     12
     13SoC-specific Required Properties:
     14
     15The following are mandatory properties for Keystone 2 66AK2G SoCs only:
     16
     17- power-domains:	Should contain a phandle to a PM domain provider node
     18			and an args specifier containing the I2C device id
     19			value. This property is as per the binding,
     20			Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml
     21
     22Recommended properties :
     23- interrupts : standard interrupt property.
     24- clock-frequency : desired I2C bus clock frequency in Hz.
     25- ti,has-pfunc: boolean; if defined, it indicates that SoC supports PFUNC
     26	registers. PFUNC registers allow to switch I2C pins to function as
     27	GPIOs, so they can be toggled manually.
     28
     29Example (enbw_cmc board):
     30	i2c@1c22000 {
     31		compatible = "ti,davinci-i2c";
     32		reg = <0x22000 0x1000>;
     33		clock-frequency = <100000>;
     34		interrupts = <15>;
     35		interrupt-parent = <&intc>;
     36		#address-cells = <1>;
     37		#size-cells = <0>;
     38
     39		dtt@48 {
     40			compatible = "national,lm75";
     41			reg = <0x48>;
     42		};
     43	};