cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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i2c-imx.yaml (2430B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/i2c/i2c-imx.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Freescale Inter IC (I2C) and High Speed Inter IC (HS-I2C) for i.MX
      8
      9maintainers:
     10  - Oleksij Rempel <o.rempel@pengutronix.de>
     11
     12allOf:
     13  - $ref: /schemas/i2c/i2c-controller.yaml#
     14
     15properties:
     16  compatible:
     17    oneOf:
     18      - const: fsl,imx1-i2c
     19      - const: fsl,imx21-i2c
     20      - const: fsl,vf610-i2c
     21      - items:
     22          - const: fsl,imx35-i2c
     23          - const: fsl,imx1-i2c
     24      - items:
     25          - const: fsl,imx7d-i2c
     26          - const: fsl,imx21-i2c
     27      - items:
     28          - enum:
     29              - fsl,imx25-i2c
     30              - fsl,imx27-i2c
     31              - fsl,imx31-i2c
     32              - fsl,imx50-i2c
     33              - fsl,imx51-i2c
     34              - fsl,imx53-i2c
     35              - fsl,imx6q-i2c
     36              - fsl,imx6sl-i2c
     37              - fsl,imx6sx-i2c
     38              - fsl,imx6sll-i2c
     39              - fsl,imx6ul-i2c
     40              - fsl,imx7s-i2c
     41              - fsl,imx8mq-i2c
     42              - fsl,imx8mm-i2c
     43              - fsl,imx8mn-i2c
     44              - fsl,imx8mp-i2c
     45          - const: fsl,imx21-i2c
     46
     47  reg:
     48    maxItems: 1
     49
     50  interrupts:
     51    maxItems: 1
     52
     53  clocks:
     54    maxItems: 1
     55
     56  clock-names:
     57    const: ipg
     58
     59  clock-frequency:
     60    minimum: 1
     61    default: 100000
     62    maximum: 400000
     63
     64  dmas:
     65    items:
     66      - description: DMA controller phandle and request line for RX
     67      - description: DMA controller phandle and request line for TX
     68
     69  dma-names:
     70    items:
     71      - const: rx
     72      - const: tx
     73
     74  sda-gpios:
     75    maxItems: 1
     76
     77  scl-gpios:
     78    maxItems: 1
     79
     80required:
     81  - compatible
     82  - reg
     83  - interrupts
     84  - clocks
     85
     86unevaluatedProperties: false
     87
     88examples:
     89  - |
     90    #include <dt-bindings/clock/imx5-clock.h>
     91    #include <dt-bindings/interrupt-controller/irq.h>
     92
     93    i2c@83fc4000 {
     94        compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
     95        reg = <0x83fc4000 0x4000>;
     96        interrupts = <63>;
     97        clocks = <&clks IMX5_CLK_I2C2_GATE>;
     98    };
     99
    100  - |
    101    #include <dt-bindings/clock/vf610-clock.h>
    102
    103    i2c@40066000 {
    104        compatible = "fsl,vf610-i2c";
    105        reg = <0x40066000 0x1000>;
    106        interrupts = <71 IRQ_TYPE_LEVEL_HIGH>;
    107        clocks = <&clks VF610_CLK_I2C0>;
    108        clock-names = "ipg";
    109        dmas = <&edma0 0 50>,
    110               <&edma0 0 51>;
    111        dma-names = "rx", "tx";
    112    };