cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

i2c-pxa-pci-ce4100.txt (2763B)

      1CE4100 I2C
      2----------
      3
      4CE4100 has one PCI device which is described as the I2C-Controller. This
      5PCI device has three PCI-bars, each bar contains a complete I2C
      6controller. So we have a total of three independent I2C-Controllers
      7which share only an interrupt line.
      8The driver is probed via the PCI-ID and is gathering the information of
      9attached devices from the devices tree.
     10Grant Likely recommended to use the ranges property to map the PCI-Bar
     11number to its physical address and to use this to find the child nodes
     12of the specific I2C controller. This were his exact words:
     13
     14       Here's where the magic happens.  Each entry in
     15       ranges describes how the parent pci address space
     16       (middle group of 3) is translated to the local
     17       address space (first group of 2) and the size of
     18       each range (last cell).  In this particular case,
     19       the first cell of the local address is chosen to be
     20       1:1 mapped to the BARs, and the second is the
     21       offset from be base of the BAR (which would be
     22       non-zero if you had 2 or more devices mapped off
     23       the same BAR)
     24
     25       ranges allows the address mapping to be described
     26       in a way that the OS can interpret without
     27       requiring custom device driver code.
     28
     29This is an example which is used on FalconFalls:
     30------------------------------------------------
     31	i2c-controller@b,2 {
     32		#address-cells = <2>;
     33		#size-cells = <1>;
     34		compatible = "pci8086,2e68.2",
     35				"pci8086,2e68",
     36				"pciclass,ff0000",
     37				"pciclass,ff00";
     38
     39		reg = <0x15a00 0x0 0x0 0x0 0x0>;
     40		interrupts = <16 1>;
     41
     42		/* as described by Grant, the first number in the group of
     43		* three is the bar number followed by the 64bit bar address
     44		* followed by size of the mapping. The bar address
     45		* requires also a valid translation in parents ranges
     46		* property.
     47		*/
     48		ranges = <0 0   0x02000000 0 0xdffe0500 0x100
     49			  1 0   0x02000000 0 0xdffe0600 0x100
     50			  2 0   0x02000000 0 0xdffe0700 0x100>;
     51
     52		i2c@0 {
     53			#address-cells = <1>;
     54			#size-cells = <0>;
     55			compatible = "intel,ce4100-i2c-controller";
     56
     57			/* The first number in the reg property is the
     58			* number of the bar
     59			*/
     60			reg = <0 0 0x100>;
     61
     62			/* This I2C controller has no devices */
     63		};
     64
     65		i2c@1 {
     66			#address-cells = <1>;
     67			#size-cells = <0>;
     68			compatible = "intel,ce4100-i2c-controller";
     69			reg = <1 0 0x100>;
     70
     71			/* This I2C controller has one gpio controller */
     72			gpio@26 {
     73				#gpio-cells = <2>;
     74				compatible = "nxp,pcf8575";
     75				reg = <0x26>;
     76				gpio-controller;
     77			};
     78		};
     79
     80		i2c@2 {
     81			#address-cells = <1>;
     82			#size-cells = <0>;
     83			compatible = "intel,ce4100-i2c-controller";
     84			reg = <2 0 0x100>;
     85
     86			gpio@26 {
     87				#gpio-cells = <2>;
     88				compatible = "nxp,pcf8575";
     89				reg = <0x26>;
     90				gpio-controller;
     91			};
     92		};
     93	};