cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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i2c-pxa.yaml (1411B)

      1# SPDX-License-Identifier: GPL-2.0-only
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/i2c/i2c-pxa.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Marvell MMP I2C controller bindings
      8
      9maintainers:
     10  - Rob Herring <robh+dt@kernel.org>
     11
     12allOf:
     13  - $ref: /schemas/i2c/i2c-controller.yaml#
     14  - if:
     15      not:
     16        required:
     17          - mrvl,i2c-polling
     18    then:
     19      required:
     20        - interrupts
     21
     22properties:
     23  compatible:
     24    enum:
     25      - mrvl,mmp-twsi
     26      - mrvl,pxa-i2c
     27      - marvell,armada-3700-i2c
     28
     29  reg:
     30    maxItems: 1
     31
     32  interrupts:
     33    maxItems: 1
     34
     35  clocks:
     36    minItems: 1
     37
     38  resets:
     39    minItems: 1
     40
     41  mrvl,i2c-polling:
     42    $ref: /schemas/types.yaml#/definitions/flag
     43    description: |
     44      Disable interrupt of i2c controller. Polling status register of i2c
     45      controller instead.
     46
     47  mrvl,i2c-fast-mode:
     48    $ref: /schemas/types.yaml#/definitions/flag
     49    description: Enable fast mode of i2c controller.
     50
     51unevaluatedProperties: false
     52
     53required:
     54  - compatible
     55  - reg
     56  - interrupts
     57  - clocks
     58  - '#address-cells'
     59  - '#size-cells'
     60
     61examples:
     62  - |
     63    #include <dt-bindings/clock/marvell,mmp2.h>
     64    i2c@d4011000 {
     65        compatible = "mrvl,mmp-twsi";
     66        reg = <0xd4011000 0x1000>;
     67        interrupts = <7>;
     68        clocks = <&soc_clocks MMP2_CLK_TWSI1>;
     69        mrvl,i2c-fast-mode;
     70        #address-cells = <1>;
     71        #size-cells = <0>;
     72    };
     73
     74...