cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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i2c-st.txt (1572B)

      1ST SSC binding, for I2C mode operation
      2
      3Required properties :
      4- compatible : Must be "st,comms-ssc-i2c" or "st,comms-ssc4-i2c"
      5- reg : Offset and length of the register set for the device
      6- interrupts : the interrupt specifier
      7- clock-names: Must contain "ssc".
      8- clocks: Must contain an entry for each name in clock-names. See the common
      9  clock bindings.
     10- A pinctrl state named "default" must be defined to set pins in mode of
     11  operation for I2C transfer.
     12
     13Optional properties :
     14- clock-frequency : Desired I2C bus clock frequency in Hz. If not specified,
     15  the default 100 kHz frequency will be used. As only Normal and Fast modes
     16  are supported, possible values are 100000 and 400000.
     17- st,i2c-min-scl-pulse-width-us : The minimum valid SCL pulse width that is
     18  allowed through the deglitch circuit. In units of us.
     19- st,i2c-min-sda-pulse-width-us : The minimum valid SDA pulse width that is
     20  allowed through the deglitch circuit. In units of us.
     21- A pinctrl state named "idle" could be defined to set pins in idle state
     22  when I2C instance is not performing a transfer.
     23- A pinctrl state named "sleep" could be defined to set pins in sleep state
     24  when driver enters in suspend.
     25
     26
     27
     28Example :
     29
     30i2c0: i2c@fed40000 {
     31	compatible	= "st,comms-ssc4-i2c";
     32	reg		= <0xfed40000 0x110>;
     33	interrupts	=  <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
     34	clocks		= <&clk_s_a0_ls CLK_ICN_REG>;
     35	clock-names	= "ssc";
     36	clock-frequency = <400000>;
     37	pinctrl-names	= "default";
     38	pinctrl-0	= <&pinctrl_i2c0_default>;
     39	st,i2c-min-scl-pulse-width-us = <0>;
     40	st,i2c-min-sda-pulse-width-us = <5>;
     41};