cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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nvidia,tegra186-bpmp-i2c.yaml (1381B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/i2c/nvidia,tegra186-bpmp-i2c.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: NVIDIA Tegra186 (and later) BPMP I2C controller
      8
      9maintainers:
     10  - Thierry Reding <thierry.reding@gmail.com>
     11  - Jon Hunter <jonathanh@nvidia.com>
     12
     13description: |
     14  In Tegra186 and later, the BPMP (Boot and Power Management Processor)
     15  owns certain HW devices, such as the I2C controller for the power
     16  management I2C bus. Software running on other CPUs must perform IPC to
     17  the BPMP in order to execute transactions on that I2C bus. This
     18  binding describes an I2C bus that is accessed in such a fashion.
     19
     20  The BPMP I2C node must be located directly inside the main BPMP node.
     21  See ../firmware/nvidia,tegra186-bpmp.yaml for details of the BPMP
     22  binding.
     23
     24  This node represents an I2C controller. See ../i2c/i2c.txt for details
     25  of the core I2C binding.
     26
     27properties:
     28  compatible:
     29    const: nvidia,tegra186-bpmp-i2c
     30
     31  nvidia,bpmp-bus-id:
     32    $ref: /schemas/types.yaml#/definitions/uint32
     33    description: Indicates the I2C bus number this DT node represents,
     34      as defined by the BPMP firmware.
     35
     36allOf:
     37  - $ref: /schemas/i2c/i2c-controller.yaml
     38
     39unevaluatedProperties: false
     40
     41required:
     42  - compatible
     43  - "#address-cells"
     44  - "#size-cells"
     45  - nvidia,bpmp-bus-id