cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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st,stm32-i2c.yaml (3955B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/i2c/st,stm32-i2c.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: I2C controller embedded in STMicroelectronics STM32 I2C platform
      8
      9maintainers:
     10  - Pierre-Yves MORDRET <pierre-yves.mordret@foss.st.com>
     11
     12allOf:
     13  - $ref: /schemas/i2c/i2c-controller.yaml#
     14  - if:
     15      properties:
     16        compatible:
     17          contains:
     18            enum:
     19              - st,stm32f7-i2c
     20              - st,stm32mp15-i2c
     21    then:
     22      properties:
     23        i2c-scl-rising-time-ns:
     24          default: 25
     25
     26        i2c-scl-falling-time-ns:
     27          default: 10
     28    else:
     29      properties:
     30        st,syscfg-fmp: false
     31
     32  - if:
     33      properties:
     34        compatible:
     35          contains:
     36            enum:
     37              - st,stm32f4-i2c
     38    then:
     39      properties:
     40        clock-frequency:
     41          enum: [100000, 400000]
     42
     43properties:
     44  compatible:
     45    enum:
     46      - st,stm32f4-i2c
     47      - st,stm32f7-i2c
     48      - st,stm32mp15-i2c
     49
     50  reg:
     51    maxItems: 1
     52
     53  interrupts:
     54    items:
     55      - description: interrupt ID for I2C event
     56      - description: interrupt ID for I2C error
     57
     58  resets:
     59    maxItems: 1
     60
     61  clocks:
     62    maxItems: 1
     63
     64  dmas:
     65    items:
     66      - description: RX DMA Channel phandle
     67      - description: TX DMA Channel phandle
     68
     69  dma-names:
     70    items:
     71      - const: rx
     72      - const: tx
     73
     74  clock-frequency:
     75    description: Desired I2C bus clock frequency in Hz. If not specified,
     76                 the default 100 kHz frequency will be used.
     77                 For STM32F7, STM32H7 and STM32MP1 SoCs, if timing parameters
     78                 match, the bus clock frequency can be from 1Hz to 1MHz.
     79    default: 100000
     80    minimum: 1
     81    maximum: 1000000
     82
     83  st,syscfg-fmp:
     84    description: Use to set Fast Mode Plus bit within SYSCFG when Fast Mode
     85      Plus speed is selected by slave.
     86    $ref: "/schemas/types.yaml#/definitions/phandle-array"
     87    items:
     88      - items:
     89          - description: phandle to syscfg
     90          - description: register offset within syscfg
     91          - description: register bitmask for FMP bit
     92
     93required:
     94  - compatible
     95  - reg
     96  - interrupts
     97  - resets
     98  - clocks
     99
    100unevaluatedProperties: false
    101
    102examples:
    103  - |
    104    #include <dt-bindings/mfd/stm32f7-rcc.h>
    105    #include <dt-bindings/clock/stm32fx-clock.h>
    106    //Example 1 (with st,stm32f4-i2c compatible)
    107      i2c@40005400 {
    108          compatible = "st,stm32f4-i2c";
    109          #address-cells = <1>;
    110          #size-cells = <0>;
    111          reg = <0x40005400 0x400>;
    112          interrupts = <31>,
    113                       <32>;
    114          resets = <&rcc 277>;
    115          clocks = <&rcc 0 149>;
    116      };
    117
    118  - |
    119    #include <dt-bindings/mfd/stm32f7-rcc.h>
    120    #include <dt-bindings/clock/stm32fx-clock.h>
    121    //Example 2 (with st,stm32f7-i2c compatible)
    122      i2c@40005800 {
    123          compatible = "st,stm32f7-i2c";
    124          #address-cells = <1>;
    125          #size-cells = <0>;
    126          reg = <0x40005800 0x400>;
    127          interrupts = <31>,
    128                       <32>;
    129          resets = <&rcc STM32F7_APB1_RESET(I2C1)>;
    130          clocks = <&rcc 1 CLK_I2C1>;
    131      };
    132
    133  - |
    134    #include <dt-bindings/mfd/stm32f7-rcc.h>
    135    #include <dt-bindings/clock/stm32fx-clock.h>
    136    //Example 3 (with st,stm32mp15-i2c compatible on stm32mp)
    137    #include <dt-bindings/interrupt-controller/arm-gic.h>
    138    #include <dt-bindings/clock/stm32mp1-clks.h>
    139    #include <dt-bindings/reset/stm32mp1-resets.h>
    140      i2c@40013000 {
    141          compatible = "st,stm32mp15-i2c";
    142          #address-cells = <1>;
    143          #size-cells = <0>;
    144          reg = <0x40013000 0x400>;
    145          interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
    146                       <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
    147          clocks = <&rcc I2C2_K>;
    148          resets = <&rcc I2C2_R>;
    149          i2c-scl-rising-time-ns = <185>;
    150          i2c-scl-falling-time-ns = <20>;
    151          st,syscfg-fmp = <&syscfg 0x4 0x2>;
    152      };