cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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silvaco,i3c-master.yaml (1144B)

      1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/i3c/silvaco,i3c-master.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Silvaco I3C master
      8
      9maintainers:
     10  - Conor Culhane <conor.culhane@silvaco.com>
     11
     12allOf:
     13  - $ref: "i3c.yaml#"
     14
     15properties:
     16  compatible:
     17    const: silvaco,i3c-master-v1
     18
     19  reg:
     20    maxItems: 1
     21
     22  interrupts:
     23    maxItems: 1
     24
     25  clocks:
     26    items:
     27      - description: system clock
     28      - description: bus clock
     29      - description: other (slower) events clock
     30
     31  clock-names:
     32    items:
     33      - const: pclk
     34      - const: fast_clk
     35      - const: slow_clk
     36
     37  resets:
     38    maxItems: 1
     39
     40required:
     41  - compatible
     42  - reg
     43  - interrupts
     44  - clock-names
     45  - clocks
     46
     47additionalProperties: true
     48
     49examples:
     50  - |
     51    i3c-master@a0000000 {
     52        compatible = "silvaco,i3c-master-v1";
     53        clocks = <&zynqmp_clk 71>, <&fclk>, <&sclk>;
     54        clock-names = "pclk", "fast_clk", "slow_clk";
     55        interrupt-parent = <&gic>;
     56        interrupts = <0 89 4>;
     57        reg = <0xa0000000 0x1000>;
     58        #address-cells = <3>;
     59        #size-cells = <0>;
     60    };