cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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brcm,iproc-static-adc.yaml (1467B)


      1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/iio/adc/brcm,iproc-static-adc.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Broadcom's IPROC Static ADC controller
      8
      9maintainers:
     10  - Raveendra Padasalagi <raveendra.padasalagi@broadcom.com>
     11
     12description: |
     13  Broadcom iProc ADC controller has 8 10bit channels
     14
     15properties:
     16  compatible:
     17    const: brcm,iproc-static-adc
     18
     19  adc-syscon:
     20    $ref: /schemas/types.yaml#/definitions/phandle
     21    description:
     22      syscon node defining physical base address of the controller and length
     23      of memory mapped region.
     24
     25  "#io-channel-cells":
     26    const: 1
     27
     28  clocks:
     29    maxItems: 1
     30
     31  clock-names:
     32    const: tsc_clk
     33
     34  interrupts:
     35    maxItems: 1
     36
     37additionalProperties: false
     38
     39required:
     40  - compatible
     41  - adc-syscon
     42  - "#io-channel-cells"
     43  - clocks
     44  - clock-names
     45  - interrupts
     46
     47examples:
     48  - |
     49    #include <dt-bindings/clock/bcm-cygnus.h>
     50    #include <dt-bindings/interrupt-controller/arm-gic.h>
     51    #include <dt-bindings/interrupt-controller/irq.h>
     52    soc {
     53        #address-cells = <1>;
     54        #size-cells = <1>;
     55
     56        adc {
     57            compatible = "brcm,iproc-static-adc";
     58            adc-syscon = <&ts_adc_syscon>;
     59            #io-channel-cells = <1>;
     60            clocks = <&asiu_clks BCM_CYGNUS_ASIU_ADC_CLK>;
     61            clock-names = "tsc_clk";
     62            interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
     63        };
     64    };
     65...