cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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nxp,imx8qxp-adc.yaml (1579B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/iio/adc/nxp,imx8qxp-adc.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: NXP IMX8QXP ADC bindings
      8
      9maintainers:
     10  - Cai Huoqing <caihuoqing@baidu.com>
     11
     12description:
     13  Supports the ADC found on the IMX8QXP SoC.
     14
     15properties:
     16  compatible:
     17    const: nxp,imx8qxp-adc
     18
     19  reg:
     20    maxItems: 1
     21
     22  interrupts:
     23    maxItems: 1
     24
     25  clocks:
     26    maxItems: 2
     27
     28  clock-names:
     29    items:
     30      - const: per
     31      - const: ipg
     32
     33  assigned-clocks:
     34    maxItems: 1
     35
     36  assigned-clock-rates:
     37    maxItems: 1
     38
     39  power-domains:
     40    maxItems: 1
     41
     42  "#io-channel-cells":
     43    const: 1
     44
     45required:
     46  - compatible
     47  - reg
     48  - interrupts
     49  - clocks
     50  - clock-names
     51  - assigned-clocks
     52  - assigned-clock-rates
     53  - power-domains
     54  - "#io-channel-cells"
     55
     56additionalProperties: false
     57
     58examples:
     59  - |
     60    #include <dt-bindings/interrupt-controller/arm-gic.h>
     61    #include <dt-bindings/firmware/imx/rsrc.h>
     62    soc {
     63        #address-cells = <2>;
     64        #size-cells = <2>;
     65        adc@5a880000 {
     66            compatible = "nxp,imx8qxp-adc";
     67            reg = <0x0 0x5a880000 0x0 0x10000>;
     68            interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
     69            clocks = <&clk IMX_SC_R_ADC_0>,
     70                     <&clk IMX_SC_R_ADC_0>;
     71            clock-names = "per", "ipg";
     72            assigned-clocks = <&clk IMX_SC_R_ADC_0>;
     73            assigned-clock-rates = <24000000>;
     74            power-domains = <&pd IMX_SC_R_ADC_0>;
     75            #io-channel-cells = <1>;
     76        };
     77    };
     78...