cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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renesas,rzg2l-adc.yaml (2809B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/iio/adc/renesas,rzg2l-adc.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Renesas RZ/G2L ADC
      8
      9maintainers:
     10  - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
     11
     12description: |
     13  A/D Converter block is a successive approximation analog-to-digital converter
     14  with a 12-bit accuracy. Up to eight analog input channels can be selected.
     15  Conversions can be performed in single or repeat mode. Result of the ADC is
     16  stored in a 32-bit data register corresponding to each channel.
     17
     18properties:
     19  compatible:
     20    items:
     21      - enum:
     22          - renesas,r9a07g044-adc   # RZ/G2L
     23          - renesas,r9a07g054-adc   # RZ/V2L
     24      - const: renesas,rzg2l-adc
     25
     26  reg:
     27    maxItems: 1
     28
     29  interrupts:
     30    maxItems: 1
     31
     32  clocks:
     33    items:
     34      - description: converter clock
     35      - description: peripheral clock
     36
     37  clock-names:
     38    items:
     39      - const: adclk
     40      - const: pclk
     41
     42  power-domains:
     43    maxItems: 1
     44
     45  resets:
     46    maxItems: 2
     47
     48  reset-names:
     49    items:
     50      - const: presetn
     51      - const: adrst-n
     52
     53  '#address-cells':
     54    const: 1
     55
     56  '#size-cells':
     57    const: 0
     58
     59required:
     60  - compatible
     61  - reg
     62  - interrupts
     63  - clocks
     64  - clock-names
     65  - power-domains
     66  - resets
     67  - reset-names
     68
     69patternProperties:
     70  "^channel@[0-7]$":
     71    $ref: "adc.yaml"
     72    type: object
     73    description: |
     74      Represents the external channels which are connected to the ADC.
     75
     76    properties:
     77      reg:
     78        description: |
     79          The channel number. It can have up to 8 channels numbered from 0 to 7.
     80        items:
     81          - minimum: 0
     82            maximum: 7
     83
     84    required:
     85      - reg
     86
     87    additionalProperties: false
     88
     89additionalProperties: false
     90
     91examples:
     92  - |
     93    #include <dt-bindings/clock/r9a07g044-cpg.h>
     94    #include <dt-bindings/interrupt-controller/arm-gic.h>
     95
     96    adc: adc@10059000 {
     97      compatible = "renesas,r9a07g044-adc", "renesas,rzg2l-adc";
     98      reg = <0x10059000 0x400>;
     99      interrupts = <GIC_SPI 347 IRQ_TYPE_EDGE_RISING>;
    100      clocks = <&cpg CPG_MOD R9A07G044_ADC_ADCLK>,
    101               <&cpg CPG_MOD R9A07G044_ADC_PCLK>;
    102      clock-names = "adclk", "pclk";
    103      power-domains = <&cpg>;
    104      resets = <&cpg R9A07G044_ADC_PRESETN>,
    105               <&cpg R9A07G044_ADC_ADRST_N>;
    106      reset-names = "presetn", "adrst-n";
    107
    108      #address-cells = <1>;
    109      #size-cells = <0>;
    110
    111      channel@0 {
    112        reg = <0>;
    113      };
    114      channel@1 {
    115        reg = <1>;
    116      };
    117      channel@2 {
    118        reg = <2>;
    119      };
    120      channel@3 {
    121        reg = <3>;
    122      };
    123      channel@4 {
    124        reg = <4>;
    125      };
    126      channel@5 {
    127        reg = <5>;
    128      };
    129      channel@6 {
    130        reg = <6>;
    131      };
    132      channel@7 {
    133        reg = <7>;
    134      };
    135    };