cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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ti,tsc2046.yaml (2340B)

      1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/iio/adc/ti,tsc2046.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Texas Instruments TSC2046 touch screen controller.
      8
      9maintainers:
     10  - Oleksij Rempel <o.rempel@pengutronix.de>
     11
     12description: |
     13  TSC2046 is a touch screen controller with 8 channels ADC.
     14
     15properties:
     16  compatible:
     17    enum:
     18      - ti,tsc2046e-adc
     19
     20  reg:
     21    maxItems: 1
     22
     23  interrupts:
     24    maxItems: 1
     25
     26  spi-max-frequency: true
     27
     28  "#io-channel-cells":
     29    const: 1
     30
     31  '#address-cells':
     32    const: 1
     33
     34  '#size-cells':
     35    const: 0
     36
     37required:
     38  - compatible
     39  - reg
     40
     41patternProperties:
     42  "^channel@[0-7]$":
     43    $ref: "adc.yaml"
     44    type: object
     45
     46    properties:
     47      reg:
     48        description: |
     49          The channel number. It can have up to 8 channels
     50        items:
     51          minimum: 0
     52          maximum: 7
     53
     54      settling-time-us: true
     55      oversampling-ratio: true
     56
     57    required:
     58      - reg
     59
     60    additionalProperties: false
     61
     62additionalProperties: false
     63
     64examples:
     65  - |
     66    #include <dt-bindings/interrupt-controller/irq.h>
     67    spi {
     68        #address-cells = <1>;
     69        #size-cells = <0>;
     70
     71        adc@0 {
     72            compatible = "ti,tsc2046e-adc";
     73            reg = <0>;
     74            spi-max-frequency = <1000000>;
     75            interrupts-extended = <&gpio3 20 IRQ_TYPE_LEVEL_LOW>;
     76            #io-channel-cells = <1>;
     77
     78            #address-cells = <1>;
     79            #size-cells = <0>;
     80
     81            channel@0 {
     82              reg = <0>;
     83            };
     84            channel@1 {
     85              reg = <1>;
     86              settling-time-us = <700>;
     87              oversampling-ratio = <5>;
     88            };
     89            channel@2 {
     90              reg = <2>;
     91            };
     92            channel@3 {
     93              reg = <3>;
     94              settling-time-us = <700>;
     95              oversampling-ratio = <5>;
     96            };
     97            channel@4 {
     98              reg = <4>;
     99              settling-time-us = <700>;
    100              oversampling-ratio = <5>;
    101            };
    102            channel@5 {
    103              reg = <5>;
    104              settling-time-us = <700>;
    105              oversampling-ratio = <5>;
    106            };
    107            channel@6 {
    108              reg = <6>;
    109            };
    110            channel@7 {
    111              reg = <7>;
    112            };
    113        };
    114    };
    115...