cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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ti,dac082s085.yaml (1433B)

      1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/iio/dac/ti,dac082s085.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Texas Instruments DAC082s085 and similar DACs
      8
      9description:
     10  A family of Texas Instruments 8/10/12-bit 2/4-channel DACs
     11
     12maintainers:
     13  - Lukas Wunner <lukas@wunner.de>
     14
     15properties:
     16  compatible:
     17    enum:
     18      - ti,dac082s085
     19      - ti,dac102s085
     20      - ti,dac122s085
     21      - ti,dac084s085
     22      - ti,dac104s085
     23      - ti,dac124s085
     24
     25  reg:
     26    maxItems: 1
     27
     28  spi-cpha: true
     29  spi-cpol:
     30    description:
     31      Must be either spi-cpha, or spi-cpol but not both.
     32
     33  vref-supply:
     34    description: Needed to provide output scaling.
     35
     36  spi-max-frequency: true
     37
     38required:
     39  - compatible
     40  - reg
     41  - vref-supply
     42
     43additionalProperties: false
     44
     45oneOf:
     46  - required:
     47      - spi-cpha
     48  - required:
     49      - spi-cpol
     50
     51examples:
     52  - |
     53    vref_2v5_reg: regulator-vref {
     54        compatible = "regulator-fixed";
     55        regulator-name = "2v5";
     56        regulator-min-microvolt = <2500000>;
     57        regulator-max-microvolt = <2500000>;
     58        regulator-always-on;
     59    };
     60    spi {
     61        #address-cells = <1>;
     62        #size-cells = <0>;
     63
     64        dac@0 {
     65            compatible = "ti,dac082s085";
     66            reg = <0>;
     67            spi-max-frequency = <40000000>;
     68            spi-cpol;
     69            vref-supply = <&vref_2v5_reg>;
     70        };
     71    };
     72...