cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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adi,adf4350.yaml (5227B)

      1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/iio/frequency/adi,adf4350.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Analog Devices ADF4350/ADF4351 wideband synthesizer
      8
      9maintainers:
     10  - Michael Hennerich <michael.hennerich@analog.com>
     11
     12properties:
     13  compatible:
     14    enum:
     15      - adi,adf4350
     16      - adi,adf4351
     17
     18  reg:
     19    maxItems: 1
     20
     21  spi-max-frequency:
     22    maximum: 20000000
     23
     24  clocks:
     25    maxItems: 1
     26    description: Clock to provide CLKIN reference clock signal.
     27
     28  clock-names:
     29    const: clkin
     30
     31  gpios:
     32    maxItems: 1
     33    description: Lock detect GPIO.
     34
     35  adi,channel-spacing:
     36    $ref: /schemas/types.yaml#/definitions/uint32
     37    description:
     38      Channel spacing in Hz (influences MODULUS).
     39
     40  adi,power-up-frequency:
     41    $ref: /schemas/types.yaml#/definitions/uint32
     42    description:
     43      If set the PLL tunes to this frequency (in Hz) on driver probe.
     44
     45  adi,reference-div-factor:
     46    $ref: /schemas/types.yaml#/definitions/uint32
     47    description:
     48      If set the driver skips dynamic calculation and uses this default
     49      value instead.
     50
     51  adi,reference-doubler-enable:
     52    $ref: /schemas/types.yaml#/definitions/flag
     53    description: Enables reference doubler.
     54
     55  adi,reference-div2-enable:
     56    $ref: /schemas/types.yaml#/definitions/flag
     57    description: Enables reference divider.
     58
     59  adi,phase-detector-polarity-positive-enable:
     60    $ref: /schemas/types.yaml#/definitions/flag
     61    description: Enables positive phase detector polarity. Default negative.
     62
     63  adi,lock-detect-precision-6ns-enable:
     64    $ref: /schemas/types.yaml#/definitions/flag
     65    description: Enables 6ns lock detect precision. Default = 10ns.
     66
     67  adi,lock-detect-function-integer-n-enable:
     68    $ref: /schemas/types.yaml#/definitions/flag
     69    description:
     70      Enables lock detect for integer-N mode. Default = factional-N mode.
     71
     72  adi,charge-pump-current:
     73    $ref: /schemas/types.yaml#/definitions/uint32
     74    description: Charge pump current in mA. Default = 2500mA.
     75
     76  adi,muxout-select:
     77    $ref: /schemas/types.yaml#/definitions/uint32
     78    minimum: 0
     79    maximum: 6
     80    description: |
     81      On chip multiplexer output selection.
     82      Valid values for the multiplexer output are:
     83      0: Three-State Output (default)
     84      1: DVDD
     85      2: DGND
     86      3: R-Counter output
     87      4: N-Divider output
     88      5: Analog lock detect
     89      6: Digital lock detect
     90
     91  adi,low-spur-mode-enable:
     92    $ref: /schemas/types.yaml#/definitions/flag
     93    description: Enables low spur mode. Default = Low noise mode.
     94
     95  adi,cycle-slip-reduction-enable:
     96    $ref: /schemas/types.yaml#/definitions/flag
     97    description: Enables cycle slip reduction.
     98
     99  adi,charge-cancellation-enable:
    100    $ref: /schemas/types.yaml#/definitions/flag
    101    description:
    102      Enabled charge pump charge cancellation for integer-N modes.
    103
    104  adi,anti-backlash-3ns-enable:
    105    $ref: /schemas/types.yaml#/definitions/flag
    106    description:
    107      Enables 3ns antibacklash pulse width for integer-N modes.
    108
    109  adi,band-select-clock-mode-high-enable:
    110    $ref: /schemas/types.yaml#/definitions/flag
    111    description: Enables faster band selection logic.
    112
    113  adi,12bit-clk-divider:
    114    $ref: /schemas/types.yaml#/definitions/uint32
    115    description:
    116      Clock divider value used when adi,12bit-clkdiv-mode != 0
    117
    118  adi,clk-divider-mode:
    119    $ref: /schemas/types.yaml#/definitions/uint32
    120    enum: [0, 1, 2]
    121    description: |
    122      Valid values for the clkdiv mode are:
    123      0: Clock divider off (default)
    124      1: Fast lock enable
    125      2: Phase resync enable
    126
    127  adi,aux-output-enable:
    128    $ref: /schemas/types.yaml#/definitions/flag
    129    description: Enables auxiliary RF output.
    130
    131  adi,aux-output-fundamental-enable:
    132    $ref: /schemas/types.yaml#/definitions/flag
    133    description: |
    134      Selects fundamental VCO output on the auxiliary RF output.
    135      Default = Output of RF dividers.
    136
    137  adi,mute-till-lock-enable:
    138    $ref: /schemas/types.yaml#/definitions/flag
    139    description: Enables Mute-Till-Lock-Detect function.
    140
    141  adi,output-power:
    142    $ref: /schemas/types.yaml#/definitions/uint32
    143    enum: [0, 1, 2, 3]
    144    description: |
    145      Output power selection.
    146      Valid values for the power mode are:
    147      0: -4dBm (default)
    148      1: -1dBm
    149      2: +2dBm
    150      3: +5dBm
    151
    152  adi,aux-output-power:
    153    $ref: /schemas/types.yaml#/definitions/uint32
    154    enum: [0, 1, 2, 3]
    155    description: |
    156      Auxiliary output power selection.
    157      Valid values for the power mode are:
    158      0: -4dBm (default)
    159      1: -1dBm
    160      2: +2dBm
    161      3: +5dBm
    162
    163additionalProperties: false
    164
    165required:
    166  - compatible
    167  - reg
    168  - clocks
    169
    170examples:
    171  - |
    172    spi {
    173        #address-cells = <1>;
    174        #size-cells = <0>;
    175
    176        pll@4 {
    177            compatible = "adi,adf4351";
    178            reg = <4>;
    179            spi-max-frequency = <10000000>;
    180            clocks = <&clk0_ad9523 9>;
    181            clock-names = "clkin";
    182            adi,channel-spacing = <10000>;
    183            adi,power-up-frequency = <2400000000>;
    184            adi,phase-detector-polarity-positive-enable;
    185            adi,charge-pump-current = <2500>;
    186            adi,output-power = <3>;
    187            adi,mute-till-lock-enable;
    188        };
    189    };
    190...