cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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adi,ad2s90.yaml (1370B)

      1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/iio/resolver/adi,ad2s90.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Analog Devices AD2S90 Resolver-to-Digital Converter
      8
      9maintainers:
     10  - Matheus Tavares <matheus.bernardino@usp.br>
     11
     12description: |
     13  Datasheet: https://www.analog.com/en/products/ad2s90.html
     14
     15properties:
     16  compatible:
     17    const: adi,ad2s90
     18
     19  reg:
     20    maxItems: 1
     21
     22  spi-max-frequency:
     23    maximum: 830000
     24    description: |
     25      Chip's max frequency, as specified in its datasheet, is 2Mhz. But a 600ns
     26      delay is expected between the application of a logic LO to CS and the
     27      application of SCLK, as also specified. And since the delay is not
     28      implemented in the spi code, to satisfy it, SCLK's period should be at
     29      most 2 * 600ns, so the max frequency should be 1 / (2 * 6e-7), which gives
     30      roughly 830000Hz.
     31
     32  spi-cpol: true
     33
     34  spi-cpha: true
     35
     36additionalProperties: false
     37
     38required:
     39  - compatible
     40  - reg
     41
     42dependencies:
     43  spi-cpol: [ spi-cpha ]
     44  spi-cpha: [ spi-cpol ]
     45
     46examples:
     47  - |
     48    spi {
     49        #address-cells = <1>;
     50        #size-cells = <0>;
     51
     52        resolver@0 {
     53            compatible = "adi,ad2s90";
     54            reg = <0>;
     55            spi-max-frequency = <830000>;
     56            spi-cpol;
     57            spi-cpha;
     58        };
     59    };
     60...