cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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hisilicon-hns-roce.txt (2741B)

      1Hisilicon RoCE DT description
      2
      3Hisilicon RoCE engine is a part of network subsystem.
      4It works depending on other part of network subsystem, such as gmac and
      5dsa fabric.
      6
      7Additional properties are described here:
      8
      9Required properties:
     10- compatible: Should contain "hisilicon,hns-roce-v1".
     11- reg: Physical base address of the RoCE driver and
     12length of memory mapped region.
     13- eth-handle: phandle, specifies a reference to a node
     14representing a ethernet device.
     15- dsaf-handle: phandle, specifies a reference to a node
     16representing a dsaf device.
     17- node_guid: a number that uniquely identifies a device or component
     18- #address-cells: must be 2
     19- #size-cells: must be 2
     20Optional properties:
     21- dma-coherent: Present if DMA operations are coherent.
     22- interrupts: should contain 32 completion event irq,1 async event irq
     23and 1 event overflow irq.
     24- interrupt-names:should be one of 34 irqs for roce device
     25  - hns-roce-comp-0 ~ hns-roce-comp-31: 32 complete event irq
     26  - hns-roce-async: 1 async event irq
     27  - hns-roce-common: named common exception warning irq
     28Example:
     29	infiniband@c4000000 {
     30			compatible = "hisilicon,hns-roce-v1";
     31			reg = <0x0 0xc4000000 0x0 0x100000>;
     32			dma-coherent;
     33			eth-handle = <&eth2 &eth3 &eth4 &eth5 &eth6 &eth7>;
     34			dsaf-handle = <&soc0_dsa>;
     35			node-guid = [00 9A CD 00 00 01 02 03];
     36			#address-cells = <2>;
     37			#size-cells = <2>;
     38			interrupt-parent = <&mbigen_dsa>;
     39			interrupts = <722 1>,
     40					<723 1>,
     41					<724 1>,
     42					<725 1>,
     43					<726 1>,
     44					<727 1>,
     45					<728 1>,
     46					<729 1>,
     47					<730 1>,
     48					<731 1>,
     49					<732 1>,
     50					<733 1>,
     51					<734 1>,
     52					<735 1>,
     53					<736 1>,
     54					<737 1>,
     55					<738 1>,
     56					<739 1>,
     57					<740 1>,
     58					<741 1>,
     59					<742 1>,
     60					<743 1>,
     61					<744 1>,
     62					<745 1>,
     63					<746 1>,
     64					<747 1>,
     65					<748 1>,
     66					<749 1>,
     67					<750 1>,
     68					<751 1>,
     69					<752 1>,
     70					<753 1>,
     71					<785 1>,
     72					<754 4>;
     73
     74			interrupt-names = "hns-roce-comp-0",
     75					"hns-roce-comp-1",
     76					"hns-roce-comp-2",
     77					"hns-roce-comp-3",
     78					"hns-roce-comp-4",
     79					"hns-roce-comp-5",
     80					"hns-roce-comp-6",
     81					"hns-roce-comp-7",
     82					"hns-roce-comp-8",
     83					"hns-roce-comp-9",
     84					"hns-roce-comp-10",
     85					"hns-roce-comp-11",
     86					"hns-roce-comp-12",
     87					"hns-roce-comp-13",
     88					"hns-roce-comp-14",
     89					"hns-roce-comp-15",
     90					"hns-roce-comp-16",
     91					"hns-roce-comp-17",
     92					"hns-roce-comp-18",
     93					"hns-roce-comp-19",
     94					"hns-roce-comp-20",
     95					"hns-roce-comp-21",
     96					"hns-roce-comp-22",
     97					"hns-roce-comp-23",
     98					"hns-roce-comp-24",
     99					"hns-roce-comp-25",
    100					"hns-roce-comp-26",
    101					"hns-roce-comp-27",
    102					"hns-roce-comp-28",
    103					"hns-roce-comp-29",
    104					"hns-roce-comp-30",
    105					"hns-roce-comp-31",
    106					"hns-roce-async",
    107					"hns-roce-common";
    108		};