cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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interconnect.txt (2806B)


      1Interconnect Provider Device Tree Bindings
      2=========================================
      3
      4The purpose of this document is to define a common set of generic interconnect
      5providers/consumers properties.
      6
      7
      8= interconnect providers =
      9
     10The interconnect provider binding is intended to represent the interconnect
     11controllers in the system. Each provider registers a set of interconnect
     12nodes, which expose the interconnect related capabilities of the interconnect
     13to consumer drivers. These capabilities can be throughput, latency, priority
     14etc. The consumer drivers set constraints on interconnect path (or endpoints)
     15depending on the use case. Interconnect providers can also be interconnect
     16consumers, such as in the case where two network-on-chip fabrics interface
     17directly.
     18
     19Required properties:
     20- compatible : contains the interconnect provider compatible string
     21- #interconnect-cells : number of cells in a interconnect specifier needed to
     22			encode the interconnect node id and optionally add a
     23			path tag
     24
     25Example:
     26
     27		snoc: interconnect@580000 {
     28			compatible = "qcom,msm8916-snoc";
     29			#interconnect-cells = <1>;
     30			reg = <0x580000 0x14000>;
     31			clock-names = "bus_clk", "bus_a_clk";
     32			clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
     33				 <&rpmcc RPM_SMD_SNOC_A_CLK>;
     34		};
     35
     36
     37= interconnect consumers =
     38
     39The interconnect consumers are device nodes which dynamically express their
     40bandwidth requirements along interconnect paths they are connected to. There
     41can be multiple interconnect providers on a SoC and the consumer may consume
     42multiple paths from different providers depending on use case and the
     43components it has to interact with.
     44
     45Required properties:
     46interconnects : Pairs of phandles and interconnect provider specifier to denote
     47	        the edge source and destination ports of the interconnect path.
     48		An optional path tag value could specified as additional argument
     49		to both endpoints and in such cases, this information will be passed
     50		to the interconnect framework to do aggregation based on the attached
     51		tag.
     52
     53Optional properties:
     54interconnect-names : List of interconnect path name strings sorted in the same
     55		     order as the interconnects property. Consumers drivers will use
     56		     interconnect-names to match interconnect paths with interconnect
     57		     specifier pairs.
     58
     59                     Reserved interconnect names:
     60			 * dma-mem: Path from the device to the main memory of
     61			            the system
     62
     63Example:
     64
     65	sdhci@7864000 {
     66		...
     67		interconnects = <&pnoc MASTER_SDCC_1 &bimc SLAVE_EBI_CH0>;
     68		interconnect-names = "sdhc-mem";
     69	};
     70
     71Example with path tags:
     72
     73	gnoc: interconnect@17900000 {
     74		...
     75		interconnect-cells = <2>;
     76	};
     77
     78	mnoc: interconnect@1380000 {
     79		...
     80		interconnect-cells = <2>;
     81	};
     82
     83	cpu@0 {
     84		...
     85		interconnects = <&gnoc MASTER_APPSS_PROC 3 &mnoc SLAVE_EBI1 3>;
     86	}