cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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allwinner,sun6i-a31-r-intc.yaml (1650B)

      1# SPDX-License-Identifier: GPL-2.0
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/interrupt-controller/allwinner,sun6i-a31-r-intc.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Allwinner A31 NMI/Wakeup Interrupt Controller Device Tree Bindings
      8
      9maintainers:
     10  - Chen-Yu Tsai <wens@csie.org>
     11  - Maxime Ripard <mripard@kernel.org>
     12
     13allOf:
     14  - $ref: /schemas/interrupt-controller.yaml#
     15
     16properties:
     17  "#interrupt-cells":
     18    const: 3
     19    description:
     20      The first cell is GIC_SPI (0), the second cell is the IRQ number, and
     21      the third cell is the trigger type as defined in interrupt.txt in this
     22      directory.
     23
     24  compatible:
     25    oneOf:
     26      - const: allwinner,sun6i-a31-r-intc
     27      - items:
     28          - enum:
     29              - allwinner,sun8i-a83t-r-intc
     30              - allwinner,sun8i-h3-r-intc
     31              - allwinner,sun50i-a64-r-intc
     32          - const: allwinner,sun6i-a31-r-intc
     33      - const: allwinner,sun50i-h6-r-intc
     34
     35  reg:
     36    maxItems: 1
     37
     38  interrupts:
     39    maxItems: 1
     40    description:
     41      The GIC interrupt labeled as "External NMI".
     42
     43  interrupt-controller: true
     44
     45required:
     46  - "#interrupt-cells"
     47  - compatible
     48  - reg
     49  - interrupts
     50  - interrupt-controller
     51
     52additionalProperties: false
     53
     54examples:
     55  - |
     56    #include <dt-bindings/interrupt-controller/arm-gic.h>
     57
     58    r_intc: interrupt-controller@1f00c00 {
     59            compatible = "allwinner,sun50i-a64-r-intc",
     60                         "allwinner,sun6i-a31-r-intc";
     61            interrupt-controller;
     62            #interrupt-cells = <3>;
     63            reg = <0x01f00c00 0x400>;
     64            interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
     65    };
     66
     67...