cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

allwinner,sun7i-a20-sc-nmi.yaml (1466B)

      1# SPDX-License-Identifier: GPL-2.0
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Allwinner A20 Non-Maskable Interrupt Controller Device Tree Bindings
      8
      9maintainers:
     10  - Chen-Yu Tsai <wens@csie.org>
     11  - Maxime Ripard <mripard@kernel.org>
     12
     13allOf:
     14  - $ref: /schemas/interrupt-controller.yaml#
     15
     16properties:
     17  "#interrupt-cells":
     18    const: 2
     19    description:
     20      The first cell is the IRQ number, the second cell the trigger
     21      type as defined in interrupt.txt in this directory.
     22
     23  compatible:
     24    oneOf:
     25      - const: allwinner,sun6i-a31-sc-nmi
     26        deprecated: true
     27      - const: allwinner,sun7i-a20-sc-nmi
     28      - items:
     29          - const: allwinner,sun8i-v3s-nmi
     30          - const: allwinner,sun9i-a80-nmi
     31      - const: allwinner,sun9i-a80-nmi
     32      - items:
     33          - const: allwinner,sun50i-a100-nmi
     34          - const: allwinner,sun9i-a80-nmi
     35
     36  reg:
     37    maxItems: 1
     38
     39  interrupts:
     40    maxItems: 1
     41
     42  interrupt-controller: true
     43
     44required:
     45  - "#interrupt-cells"
     46  - compatible
     47  - reg
     48  - interrupts
     49  - interrupt-controller
     50
     51unevaluatedProperties: false
     52
     53examples:
     54  - |
     55    interrupt-controller@1c00030 {
     56        compatible = "allwinner,sun7i-a20-sc-nmi";
     57        interrupt-controller;
     58        #interrupt-cells = <2>;
     59        reg = <0x01c00030 0x0c>;
     60        interrupt-parent = <&gic>;
     61        interrupts = <0 0 4>;
     62    };
     63
     64...