cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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arm,vic.yaml (2206B)

      1# SPDX-License-Identifier: GPL-2.0
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/interrupt-controller/arm,vic.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: ARM Vectored Interrupt Controller
      8
      9maintainers:
     10  - Rob Herring <robh@kernel.org>
     11
     12description: |+
     13  One or more Vectored Interrupt Controllers (VIC's) can be connected in an
     14  ARM system for interrupt routing.  For multiple controllers they can either
     15  be nested or have the outputs wire-OR'd together.
     16
     17allOf:
     18  - $ref: /schemas/interrupt-controller.yaml#
     19
     20properties:
     21  compatible:
     22    enum:
     23      - arm,pl190-vic
     24      - arm,pl192-vic
     25      - arm,versatile-vic
     26
     27  interrupt-controller: true
     28
     29  "#interrupt-cells":
     30    const: 1
     31    description:
     32      The number of cells to define the interrupts.  It must be 1 as the
     33      VIC has no configuration options for interrupt sources. The single
     34      cell defines the interrupt number.
     35
     36  reg:
     37    maxItems: 1
     38
     39  interrupts:
     40    maxItems: 1
     41
     42  valid-mask:
     43    description:
     44      A one cell big bit mask of valid interrupt sources. Each bit
     45      represents single interrupt source, starting from source 0 at
     46      LSb and ending at source 31 at MSb. A bit that is set means
     47      that the source is wired and clear means otherwise. If unspecified,
     48      defaults to all valid.
     49    $ref: /schemas/types.yaml#/definitions/uint32
     50
     51  valid-wakeup-mask:
     52    description:
     53      A one cell big bit mask of interrupt sources that can be configured
     54      as wake up source for the system. Order of bits is the same as for
     55      valid-mask property. A set bit means that this interrupt source
     56      can be configured as a wake up source for the system. If unspecied,
     57      defaults to all interrupt sources configurable as wake up sources.
     58    $ref: /schemas/types.yaml#/definitions/uint32
     59
     60required:
     61  - compatible
     62  - reg
     63  - interrupt-controller
     64  - "#interrupt-cells"
     65
     66additionalProperties: false
     67
     68examples:
     69  - |
     70    // PL192 VIC
     71    vic0: interrupt-controller@60000 {
     72      compatible = "arm,pl192-vic";
     73      interrupt-controller;
     74      #interrupt-cells = <1>;
     75      reg = <0x60000 0x1000>;
     76
     77      valid-mask = <0xffffff7f>;
     78      valid-wakeup-mask = <0x0000ff7f>;
     79    };
     80
     81...