cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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aspeed,ast2400-vic.txt (720B)

      1Aspeed Vectored Interrupt Controller
      2
      3These bindings are for the Aspeed interrupt controller. The AST2400 and
      4AST2500 SoC families include a legacy register layout before a re-designed
      5layout, but the bindings do not prescribe the use of one or the other.
      6
      7Required properties:
      8
      9- compatible : "aspeed,ast2400-vic"
     10               "aspeed,ast2500-vic"
     11
     12- interrupt-controller : Identifies the node as an interrupt controller
     13- #interrupt-cells : Specifies the number of cells needed to encode an
     14  interrupt source. The value shall be 1.
     15
     16Example:
     17
     18 vic: interrupt-controller@1e6c0080 {
     19      compatible = "aspeed,ast2400-vic";
     20      interrupt-controller;
     21      #interrupt-cells = <1>;
     22      reg = <0x1e6c0080 0x80>;
     23 };