cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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atmel,aic.txt (1417B)

      1* Advanced Interrupt Controller (AIC)
      2
      3Required properties:
      4- compatible: Should be:
      5    - "atmel,<chip>-aic" where  <chip> can be "at91rm9200", "sama5d2",
      6      "sama5d3" or "sama5d4"
      7    - "microchip,<chip>-aic" where <chip> can be "sam9x60"
      8
      9- interrupt-controller: Identifies the node as an interrupt controller.
     10- #interrupt-cells: The number of cells to define the interrupts. It should be 3.
     11  The first cell is the IRQ number (aka "Peripheral IDentifier" on datasheet).
     12  The second cell is used to specify flags:
     13    bits[3:0] trigger type and level flags:
     14      1 = low-to-high edge triggered.
     15      2 = high-to-low edge triggered.
     16      4 = active high level-sensitive.
     17      8 = active low level-sensitive.
     18      Valid combinations are 1, 2, 3, 4, 8.
     19      Default flag for internal sources should be set to 4 (active high).
     20  The third cell is used to specify the irq priority from 0 (lowest) to 7
     21  (highest).
     22- reg: Should contain AIC registers location and length
     23- atmel,external-irqs: u32 array of external irqs.
     24
     25Examples:
     26	/*
     27	 * AIC
     28	 */
     29	aic: interrupt-controller@fffff000 {
     30		compatible = "atmel,at91rm9200-aic";
     31		interrupt-controller;
     32		#interrupt-cells = <3>;
     33		reg = <0xfffff000 0x200>;
     34	};
     35
     36	/*
     37	 * An interrupt generating device that is wired to an AIC.
     38	 */
     39	dma: dma-controller@ffffec00 {
     40		compatible = "atmel,at91sam9g45-dma";
     41		reg = <0xffffec00 0x200>;
     42		interrupts = <21 4 5>;
     43	};