brcm,bcm6345-l1-intc.txt (1967B)
1Broadcom BCM6345-style Level 1 interrupt controller 2 3This block is a first level interrupt controller that is typically connected 4directly to one of the HW INT lines on each CPU. 5 6Key elements of the hardware design include: 7 8- 32, 64 or 128 incoming level IRQ lines 9 10- Most onchip peripherals are wired directly to an L1 input 11 12- A separate instance of the register set for each CPU, allowing individual 13 peripheral IRQs to be routed to any CPU 14 15- Contains one or more enable/status word pairs per CPU 16 17- No atomic set/clear operations 18 19- No polarity/level/edge settings 20 21- No FIFO or priority encoder logic; software is expected to read all 22 2-4 status words to determine which IRQs are pending 23 24Required properties: 25 26- compatible: should be "brcm,bcm<soc>-l1-intc", "brcm,bcm6345-l1-intc" 27- reg: specifies the base physical address and size of the registers; 28 the number of supported IRQs is inferred from the size argument 29- interrupt-controller: identifies the node as an interrupt controller 30- #interrupt-cells: specifies the number of cells needed to encode an interrupt 31 source, should be 1. 32- interrupts: specifies the interrupt line(s) in the interrupt-parent controller 33 node; valid values depend on the type of parent interrupt controller 34 35If multiple reg ranges and interrupt-parent entries are present on an SMP 36system, the driver will allow IRQ SMP affinity to be set up through the 37/proc/irq/ interface. In the simplest possible configuration, only one 38reg range and one interrupt-parent is needed. 39 40The driver operates in native CPU endian by default, there is no support for 41specifying an alternative endianness. 42 43Example: 44 45periph_intc: interrupt-controller@10000000 { 46 compatible = "brcm,bcm63168-l1-intc", "brcm,bcm6345-l1-intc"; 47 reg = <0x10000020 0x20>, 48 <0x10000040 0x20>; 49 50 interrupt-controller; 51 #interrupt-cells = <1>; 52 53 interrupt-parent = <&cpu_intc>; 54 interrupts = <2>, <3>; 55};