cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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fsl,ls-scfg-msi.txt (1051B)


      1* Freescale Layerscape SCFG PCIe MSI controller
      2
      3Required properties:
      4
      5- compatible: should be "fsl,<soc-name>-msi" to identify
      6	      Layerscape PCIe MSI controller block such as:
      7              "fsl,ls1021a-msi"
      8              "fsl,ls1043a-msi"
      9              "fsl,ls1046a-msi"
     10              "fsl,ls1043a-v1.1-msi"
     11              "fsl,ls1012a-msi"
     12- msi-controller: indicates that this is a PCIe MSI controller node
     13- reg: physical base address of the controller and length of memory mapped.
     14- interrupts: an interrupt to the parent interrupt controller.
     15
     16This interrupt controller hardware is a second level interrupt controller that
     17is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
     18platforms. If interrupt-parent is not provided, the default parent interrupt
     19controller will be used.
     20Each PCIe node needs to have property msi-parent that points to
     21MSI controller node
     22
     23Examples:
     24
     25	msi1: msi-controller@1571000 {
     26		compatible = "fsl,ls1043a-msi";
     27		reg = <0x0 0x1571000 0x0 0x8>,
     28		msi-controller;
     29		interrupts = <0 116 0x4>;
     30	};