cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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ingenic,intc.yaml (1426B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/interrupt-controller/ingenic,intc.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Ingenic SoCs interrupt controller devicetree bindings
      8
      9maintainers:
     10  - Paul Cercueil <paul@crapouillou.net>
     11
     12properties:
     13  $nodename:
     14    pattern: "^interrupt-controller@[0-9a-f]+$"
     15
     16  compatible:
     17    oneOf:
     18      - enum:
     19          - ingenic,jz4740-intc
     20          - ingenic,jz4760-intc
     21          - ingenic,jz4780-intc
     22      - items:
     23          - enum:
     24              - ingenic,jz4775-intc
     25              - ingenic,jz4770-intc
     26              - ingenic,jz4760b-intc
     27          - const: ingenic,jz4760-intc
     28      - items:
     29          - const: ingenic,x1000-intc
     30          - const: ingenic,jz4780-intc
     31      - items:
     32          - const: ingenic,jz4725b-intc
     33          - const: ingenic,jz4740-intc
     34
     35  "#interrupt-cells":
     36    const: 1
     37
     38  reg:
     39    maxItems: 1
     40
     41  interrupts:
     42    maxItems: 1
     43
     44  interrupt-controller: true
     45
     46required:
     47  - compatible
     48  - reg
     49  - interrupts
     50  - "#interrupt-cells"
     51  - interrupt-controller
     52
     53additionalProperties: false
     54
     55examples:
     56  - |
     57    intc: interrupt-controller@10001000 {
     58      compatible = "ingenic,jz4770-intc", "ingenic,jz4760-intc";
     59      reg = <0x10001000 0x40>;
     60
     61      interrupt-controller;
     62      #interrupt-cells = <1>;
     63
     64      interrupt-parent = <&cpuintc>;
     65      interrupts = <2>;
     66    };