cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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loongson,htvec.yaml (1352B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: "http://devicetree.org/schemas/interrupt-controller/loongson,htvec.yaml#"
      5$schema: "http://devicetree.org/meta-schemas/core.yaml#"
      6
      7title: Loongson-3 HyperTransport Interrupt Vector Controller
      8
      9maintainers:
     10  - Jiaxun Yang <jiaxun.yang@flygoat.com>
     11
     12description:
     13  This interrupt controller is found in the Loongson-3 family of chips for
     14  receiving vectorized interrupts from PCH's interrupt controller.
     15
     16properties:
     17  compatible:
     18    const: loongson,htvec-1.0
     19
     20  reg:
     21    maxItems: 1
     22
     23  interrupts:
     24    minItems: 1
     25    maxItems: 8
     26    description: Eight parent interrupts that receive chained interrupts.
     27
     28  interrupt-controller: true
     29
     30  '#interrupt-cells':
     31    const: 1
     32
     33required:
     34  - compatible
     35  - reg
     36  - interrupts
     37  - interrupt-controller
     38  - '#interrupt-cells'
     39
     40additionalProperties: false
     41
     42examples:
     43  - |
     44    #include <dt-bindings/interrupt-controller/irq.h>
     45    htvec: interrupt-controller@fb000080 {
     46      compatible = "loongson,htvec-1.0";
     47      reg = <0xfb000080 0x40>;
     48      interrupt-controller;
     49      #interrupt-cells = <1>;
     50
     51      interrupt-parent = <&liointc>;
     52      interrupts = <24 IRQ_TYPE_LEVEL_HIGH>,
     53                    <25 IRQ_TYPE_LEVEL_HIGH>,
     54                    <26 IRQ_TYPE_LEVEL_HIGH>,
     55                    <27 IRQ_TYPE_LEVEL_HIGH>;
     56    };
     57...