cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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loongson,pch-pic.yaml (1312B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: "http://devicetree.org/schemas/interrupt-controller/loongson,pch-pic.yaml#"
      5$schema: "http://devicetree.org/meta-schemas/core.yaml#"
      6
      7title: Loongson PCH PIC Controller
      8
      9maintainers:
     10  - Jiaxun Yang <jiaxun.yang@flygoat.com>
     11
     12description:
     13  This interrupt controller is found in the Loongson LS7A family of PCH for
     14  transforming interrupts from on-chip devices into HyperTransport vectorized
     15  interrupts.
     16
     17properties:
     18  compatible:
     19    const: loongson,pch-pic-1.0
     20
     21  reg:
     22    maxItems: 1
     23
     24  loongson,pic-base-vec:
     25    description:
     26      u32 value of the base of parent HyperTransport vector allocated
     27      to PCH PIC.
     28    $ref: "/schemas/types.yaml#/definitions/uint32"
     29    minimum: 0
     30    maximum: 192
     31
     32  interrupt-controller: true
     33
     34  '#interrupt-cells':
     35    const: 2
     36
     37required:
     38  - compatible
     39  - reg
     40  - loongson,pic-base-vec
     41  - interrupt-controller
     42  - '#interrupt-cells'
     43
     44additionalProperties: false
     45
     46examples:
     47  - |
     48    #include <dt-bindings/interrupt-controller/irq.h>
     49    pic: interrupt-controller@10000000 {
     50      compatible = "loongson,pch-pic-1.0";
     51      reg = <0x10000000 0x400>;
     52      interrupt-controller;
     53      #interrupt-cells = <2>;
     54      loongson,pic-base-vec = <64>;
     55      interrupt-parent = <&htvec>;
     56    };
     57...