cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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marvell,armada-8k-pic.txt (887B)

      1Marvell Armada 7K/8K PIC Interrupt controller
      2---------------------------------------------
      3
      4This is the Device Tree binding for the PIC, a secondary interrupt
      5controller available on the Marvell Armada 7K/8K ARM64 SoCs, and
      6typically connected to the GIC as the primary interrupt controller.
      7
      8Required properties:
      9- compatible: should be "marvell,armada-8k-pic"
     10- interrupt-controller: identifies the node as an interrupt controller
     11- #interrupt-cells: the number of cells to define interrupts on this
     12  controller. Should be 1
     13- reg: the register area for the PIC interrupt controller
     14- interrupts: the interrupt to the primary interrupt controller,
     15  typically the GIC
     16
     17Example:
     18
     19	pic: interrupt-controller@3f0100 {
     20		compatible = "marvell,armada-8k-pic";
     21		reg = <0x3f0100 0x10>;
     22		#interrupt-cells = <1>;
     23		interrupt-controller;
     24		interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
     25	};