cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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mscc,ocelot-icpu-intr.yaml (1323B)


      1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: "http://devicetree.org/schemas/interrupt-controller/mscc,ocelot-icpu-intr.yaml#"
      5$schema: "http://devicetree.org/meta-schemas/core.yaml#"
      6
      7title: Microsemi Ocelot SoC ICPU Interrupt Controller
      8
      9maintainers:
     10  - Alexandre Belloni <alexandre.belloni@bootlin.com>
     11
     12allOf:
     13  - $ref: /schemas/interrupt-controller.yaml#
     14
     15description: |
     16  the Microsemi Ocelot interrupt controller that is part of the
     17  ICPU. It is connected directly to the MIPS core interrupt
     18  controller.
     19
     20properties:
     21  compatible:
     22    items:
     23      - enum:
     24          - mscc,jaguar2-icpu-intr
     25          - mscc,luton-icpu-intr
     26          - mscc,ocelot-icpu-intr
     27          - mscc,serval-icpu-intr
     28
     29
     30  '#interrupt-cells':
     31    const: 1
     32
     33  '#address-cells':
     34    const: 0
     35
     36  interrupt-controller: true
     37
     38  reg:
     39    maxItems: 1
     40
     41  interrupts:
     42    maxItems: 1
     43
     44required:
     45  - compatible
     46  - '#interrupt-cells'
     47  - '#address-cells'
     48  - interrupt-controller
     49  - reg
     50
     51additionalProperties: false
     52
     53examples:
     54  - |
     55    intc: interrupt-controller@70000070 {
     56        compatible = "mscc,ocelot-icpu-intr";
     57        reg = <0x70000070 0x70>;
     58        #interrupt-cells = <1>;
     59        #address-cells = <0>;
     60        interrupt-controller;
     61        interrupt-parent = <&cpuintc>;
     62        interrupts = <2>;
     63    };
     64...