cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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msi-controller.yaml (1405B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/interrupt-controller/msi-controller.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: MSI controller
      8
      9maintainers:
     10  - Marc Zyngier <maz@kernel.org>
     11
     12description: |
     13  An MSI controller signals interrupts to a CPU when a write is made
     14  to an MMIO address by some master. An MSI controller may feature a
     15  number of doorbells.
     16
     17properties:
     18  "#msi-cells":
     19    description: |
     20      The number of cells in an msi-specifier, required if not zero.
     21
     22      Typically this will encode information related to sideband data,
     23      and will not encode doorbells or payloads as these can be
     24      configured dynamically.
     25
     26      The meaning of the msi-specifier is defined by the device tree
     27      binding of the specific MSI controller.
     28    enum: [0, 1]
     29
     30  msi-controller:
     31    description:
     32      Identifies the node as an MSI controller.
     33    $ref: /schemas/types.yaml#/definitions/flag
     34
     35  msi-ranges:
     36    description:
     37      A list of <phandle intspec span> tuples, where "phandle" is the
     38      parent interrupt controller, "intspec" is the starting/base
     39      interrupt specifier and "span" is the size of the
     40      range. Multiple ranges can be provided.
     41    $ref: /schemas/types.yaml#/definitions/phandle-array
     42
     43dependencies:
     44  "#msi-cells": [ msi-controller ]
     45
     46additionalProperties: true