cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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opencores,or1k-pic.txt (797B)


      1OpenRISC 1000 Programmable Interrupt Controller
      2
      3Required properties:
      4
      5- compatible : should be "opencores,or1k-pic-level" for variants with
      6  level triggered interrupt lines, "opencores,or1k-pic-edge" for variants with
      7  edge triggered interrupt lines or "opencores,or1200-pic" for machines
      8  with the non-spec compliant or1200 type implementation.
      9
     10  "opencores,or1k-pic" is also provided as an alias to "opencores,or1200-pic",
     11  but this is only for backwards compatibility.
     12
     13- interrupt-controller : Identifies the node as an interrupt controller
     14- #interrupt-cells : Specifies the number of cells needed to encode an
     15  interrupt source. The value shall be 1.
     16
     17Example:
     18
     19intc: interrupt-controller {
     20	compatible = "opencores,or1k-pic-level";
     21	interrupt-controller;
     22	#interrupt-cells = <1>;
     23};