cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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openrisc,ompic.txt (723B)


      1Open Multi-Processor Interrupt Controller
      2
      3Required properties:
      4
      5- compatible : This should be "openrisc,ompic"
      6- reg : Specifies base physical address and size of the register space. The
      7  size is based on the number of cores the controller has been configured
      8  to handle, this should be set to 8 bytes per cpu core.
      9- interrupt-controller : Identifies the node as an interrupt controller.
     10- #interrupt-cells : This should be set to 0 as this will not be an irq
     11  parent.
     12- interrupts : Specifies the interrupt line to which the ompic is wired.
     13
     14Example:
     15
     16ompic: interrupt-controller@98000000 {
     17	compatible = "openrisc,ompic";
     18	reg = <0x98000000 16>;
     19	interrupt-controller;
     20	#interrupt-cells = <0>;
     21	interrupts = <1>;
     22};