cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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qca,ath79-misc-intc.txt (1335B)

      1Binding for Qualcomm Atheros AR7xxx/AR9XXX MISC interrupt controller
      2
      3The MISC interrupt controller is a secondary controller for lower priority
      4interrupt.
      5
      6Required Properties:
      7- compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-misc-intc" or
      8  "qca,<soctype>-cpu-intc", "qca,ar7240-misc-intc"
      9- reg: Base address and size of the controllers memory area
     10- interrupts: Interrupt specifier for the controllers interrupt.
     11- interrupt-controller : Identifies the node as an interrupt controller
     12- #interrupt-cells : Specifies the number of cells needed to encode interrupt
     13		     source, should be 1
     14
     15Compatible fallback depends on the SoC. Use ar7100 for ar71xx and ar913x,
     16use ar7240 for all other SoCs.
     17
     18Please refer to interrupts.txt in this directory for details of the common
     19Interrupt Controllers bindings used by client devices.
     20
     21Example:
     22
     23	interrupt-controller@18060010 {
     24		compatible = "qca,ar9132-misc-intc", "qca,ar7100-misc-intc";
     25		reg = <0x18060010 0x4>;
     26
     27		interrupt-parent = <&cpuintc>;
     28		interrupts = <6>;
     29
     30		interrupt-controller;
     31		#interrupt-cells = <1>;
     32	};
     33
     34Another example:
     35
     36	interrupt-controller@18060010 {
     37		compatible = "qca,ar9331-misc-intc", qca,ar7240-misc-intc";
     38		reg = <0x18060010 0x4>;
     39
     40		interrupt-parent = <&cpuintc>;
     41		interrupts = <6>;
     42
     43		interrupt-controller;
     44		#interrupt-cells = <1>;
     45	};