cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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renesas,intc-irqpin.yaml (2926B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/interrupt-controller/renesas,intc-irqpin.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Renesas Interrupt Controller (INTC) for external pins
      8
      9maintainers:
     10  - Geert Uytterhoeven <geert+renesas@glider.be>
     11
     12properties:
     13  compatible:
     14    items:
     15      - enum:
     16          - renesas,intc-irqpin-r8a7740  # R-Mobile A1
     17          - renesas,intc-irqpin-r8a7778  # R-Car M1A
     18          - renesas,intc-irqpin-r8a7779  # R-Car H1
     19          - renesas,intc-irqpin-sh73a0   # SH-Mobile AG5
     20      - const: renesas,intc-irqpin
     21
     22  reg:
     23    minItems: 5
     24    items:
     25      - description: Interrupt control register
     26      - description: Interrupt priority register
     27      - description: Interrupt source register
     28      - description: Interrupt mask register
     29      - description: Interrupt mask clear register
     30      - description: Interrupt control register for ICR0 with IRLM0 bit
     31
     32  interrupt-controller: true
     33
     34  '#interrupt-cells':
     35    const: 2
     36
     37  interrupts:
     38    minItems: 1
     39    maxItems: 8
     40
     41  sense-bitfield-width:
     42    $ref: /schemas/types.yaml#/definitions/uint32
     43    enum: [2, 4]
     44    default: 4
     45    description:
     46      Width of a single sense bitfield in the SENSE register, if different from the
     47      default.
     48
     49  control-parent:
     50    type: boolean
     51    description:
     52      Disable and enable interrupts on the parent interrupt controller, needed for some
     53      broken implementations.
     54
     55  clocks:
     56    maxItems: 1
     57
     58  power-domains:
     59    maxItems: 1
     60
     61required:
     62  - compatible
     63  - reg
     64  - interrupt-controller
     65  - '#interrupt-cells'
     66  - interrupts
     67
     68if:
     69  properties:
     70    compatible:
     71      contains:
     72        enum:
     73          - renesas,intc-irqpin-r8a7740
     74          - renesas,intc-irqpin-sh73a0
     75then:
     76  required:
     77    - clocks
     78    - power-domains
     79
     80additionalProperties: false
     81
     82examples:
     83  - |
     84    #include <dt-bindings/clock/r8a7740-clock.h>
     85    #include <dt-bindings/interrupt-controller/arm-gic.h>
     86    #include <dt-bindings/interrupt-controller/irq.h>
     87
     88    irqpin1: interrupt-controller@e6900004 {
     89        compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
     90        reg = <0xe6900004 4>,
     91              <0xe6900014 4>,
     92              <0xe6900024 1>,
     93              <0xe6900044 1>,
     94              <0xe6900064 1>;
     95        interrupt-controller;
     96        #interrupt-cells = <2>;
     97        interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
     98                     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
     99                     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
    100                     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
    101                     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
    102                     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
    103                     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
    104                     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
    105        clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
    106        power-domains = <&pd_a4s>;
    107    };