cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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renesas,irqc.yaml (2711B)

      1# SPDX-License-Identifier: GPL-2.0
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/interrupt-controller/renesas,irqc.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: DT bindings for the R-Mobile/R-Car/RZ/G interrupt controller
      8
      9maintainers:
     10  - Geert Uytterhoeven <geert+renesas@glider.be>
     11
     12properties:
     13  compatible:
     14    items:
     15      - enum:
     16          - renesas,irqc-r8a73a4        # R-Mobile APE6
     17          - renesas,irqc-r8a7742        # RZ/G1H
     18          - renesas,irqc-r8a7743        # RZ/G1M
     19          - renesas,irqc-r8a7744        # RZ/G1N
     20          - renesas,irqc-r8a7745        # RZ/G1E
     21          - renesas,irqc-r8a77470       # RZ/G1C
     22          - renesas,irqc-r8a7790        # R-Car H2
     23          - renesas,irqc-r8a7791        # R-Car M2-W
     24          - renesas,irqc-r8a7792        # R-Car V2H
     25          - renesas,irqc-r8a7793        # R-Car M2-N
     26          - renesas,irqc-r8a7794        # R-Car E2
     27          - renesas,intc-ex-r8a774a1    # RZ/G2M
     28          - renesas,intc-ex-r8a774b1    # RZ/G2N
     29          - renesas,intc-ex-r8a774c0    # RZ/G2E
     30          - renesas,intc-ex-r8a774e1    # RZ/G2H
     31          - renesas,intc-ex-r8a7795     # R-Car H3
     32          - renesas,intc-ex-r8a7796     # R-Car M3-W
     33          - renesas,intc-ex-r8a77961    # R-Car M3-W+
     34          - renesas,intc-ex-r8a77965    # R-Car M3-N
     35          - renesas,intc-ex-r8a77970    # R-Car V3M
     36          - renesas,intc-ex-r8a77980    # R-Car V3H
     37          - renesas,intc-ex-r8a77990    # R-Car E3
     38          - renesas,intc-ex-r8a77995    # R-Car D3
     39          - renesas,intc-ex-r8a779a0    # R-Car V3U
     40      - const: renesas,irqc
     41
     42  '#interrupt-cells':
     43    # an interrupt index and flags, as defined in interrupts.txt in
     44    # this directory
     45    const: 2
     46
     47  interrupt-controller: true
     48
     49  reg:
     50    maxItems: 1
     51
     52  interrupts:
     53    minItems: 1
     54    maxItems: 32
     55
     56  clocks:
     57    maxItems: 1
     58
     59  power-domains:
     60    maxItems: 1
     61
     62  resets:
     63    maxItems: 1
     64
     65required:
     66  - compatible
     67  - '#interrupt-cells'
     68  - interrupt-controller
     69  - reg
     70  - interrupts
     71  - clocks
     72
     73additionalProperties: false
     74
     75examples:
     76  - |
     77    #include <dt-bindings/clock/r8a7790-cpg-mssr.h>
     78    #include <dt-bindings/interrupt-controller/arm-gic.h>
     79    #include <dt-bindings/interrupt-controller/irq.h>
     80
     81    irqc0: interrupt-controller@e61c0000 {
     82        compatible = "renesas,irqc-r8a7790", "renesas,irqc";
     83        #interrupt-cells = <2>;
     84        interrupt-controller;
     85        reg = <0xe61c0000 0x200>;
     86        interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
     87                     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
     88                     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
     89                     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
     90        clocks = <&cpg CPG_MOD 407>;
     91    };