cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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renesas,rza1-irqc.yaml (2189B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/interrupt-controller/renesas,rza1-irqc.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Renesas RZ/A1 Interrupt Controller
      8
      9maintainers:
     10  - Chris Brandt <chris.brandt@renesas.com>
     11  - Geert Uytterhoeven <geert+renesas@glider.be>
     12
     13description: |
     14  The RZ/A1 Interrupt Controller is a front-end for the GIC found on Renesas RZ/A1 and
     15  RZ/A2 SoCs:
     16    - IRQ sense select for 8 external interrupts, 1:1-mapped to 8 GIC SPI interrupts,
     17    - NMI edge select.
     18
     19allOf:
     20  - $ref: /schemas/interrupt-controller.yaml#
     21
     22properties:
     23  compatible:
     24    items:
     25      - enum:
     26          - renesas,r7s72100-irqc # RZ/A1H
     27          - renesas,r7s9210-irqc  # RZ/A2M
     28      - const: renesas,rza1-irqc
     29
     30  '#interrupt-cells':
     31    const: 2
     32
     33  '#address-cells':
     34    const: 0
     35
     36  interrupt-controller: true
     37
     38  reg:
     39    maxItems: 1
     40
     41  interrupt-map:
     42    maxItems: 8
     43    description: Specifies the mapping from external interrupts to GIC interrupts.
     44
     45  interrupt-map-mask:
     46    items:
     47      - const: 7
     48      - const: 0
     49
     50required:
     51  - compatible
     52  - '#interrupt-cells'
     53  - '#address-cells'
     54  - interrupt-controller
     55  - reg
     56  - interrupt-map
     57  - interrupt-map-mask
     58
     59additionalProperties: false
     60
     61examples:
     62  - |
     63    #include <dt-bindings/interrupt-controller/arm-gic.h>
     64    irqc: interrupt-controller@fcfef800 {
     65            compatible = "renesas,r7s72100-irqc", "renesas,rza1-irqc";
     66            #interrupt-cells = <2>;
     67            #address-cells = <0>;
     68            interrupt-controller;
     69            reg = <0xfcfef800 0x6>;
     70            interrupt-map =
     71                    <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
     72                    <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
     73                    <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
     74                    <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
     75                    <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
     76                    <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
     77                    <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
     78                    <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
     79            interrupt-map-mask = <7 0>;
     80    };