cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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samsung,exynos4210-combiner.yaml (3269B)

      1# SPDX-License-Identifier: GPL-2.0
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/interrupt-controller/samsung,exynos4210-combiner.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Samsung Exynos SoC Interrupt Combiner Controller
      8
      9maintainers:
     10  - Krzysztof Kozlowski <krzk@kernel.org>
     11
     12description: |
     13  Samsung's Exynos4 architecture includes a interrupt combiner controller which
     14  can combine interrupt sources as a group and provide a single interrupt
     15  request for the group. The interrupt request from each group are connected to
     16  a parent interrupt controller, such as GIC in case of Exynos4210.
     17
     18  The interrupt combiner controller consists of multiple combiners. Up to eight
     19  interrupt sources can be connected to a combiner. The combiner outputs one
     20  combined interrupt for its eight interrupt sources. The combined interrupt is
     21  usually connected to a parent interrupt controller.
     22
     23  A single node in the device tree is used to describe the interrupt combiner
     24  controller module (which includes multiple combiners). A combiner in the
     25  interrupt controller module shares config/control registers with other
     26  combiners. For example, a 32-bit interrupt enable/disable config register can
     27  accommodate up to 4 interrupt combiners (with each combiner supporting up to
     28  8 interrupt sources).
     29
     30allOf:
     31  - $ref: /schemas/interrupt-controller.yaml#
     32
     33properties:
     34  compatible:
     35    const: samsung,exynos4210-combiner
     36
     37  interrupt-controller: true
     38
     39  interrupts:
     40    minItems: 8
     41    maxItems: 32
     42
     43  "#interrupt-cells":
     44    description: |
     45      The meaning of the cells are:
     46        * First Cell: Combiner Group Number.
     47        * Second Cell: Interrupt number within the group.
     48    const: 2
     49
     50  reg:
     51    maxItems: 1
     52
     53  samsung,combiner-nr:
     54    description: |
     55      The number of interrupt combiners supported.  Should match number
     56      of interrupts set in "interrupts" property.
     57    $ref: /schemas/types.yaml#/definitions/uint32
     58    minimum: 8
     59    maximum: 32
     60    default: 16
     61
     62required:
     63  - compatible
     64  - interrupt-controller
     65  - interrupts
     66  - "#interrupt-cells"
     67  - reg
     68
     69additionalProperties: false
     70
     71examples:
     72  - |
     73    #include <dt-bindings/interrupt-controller/arm-gic.h>
     74
     75    interrupt-controller@10440000 {
     76        compatible = "samsung,exynos4210-combiner";
     77        interrupt-controller;
     78        #interrupt-cells = <2>;
     79        reg = <0x10440000 0x1000>;
     80        interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
     81                     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
     82                     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
     83                     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
     84                     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
     85                     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
     86                     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
     87                     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
     88                     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
     89                     <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
     90                     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
     91                     <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
     92                     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
     93                     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
     94                     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
     95                     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
     96    };