cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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technologic,ts4800.txt (605B)

      1TS-4800 FPGA interrupt controller
      2
      3TS-4800 FPGA has an internal interrupt controller. When one of the
      4interrupts is triggered, the SoC is notified, usually using a GPIO as
      5parent interrupt source.
      6
      7Required properties:
      8- compatible: should be "technologic,ts4800-irqc"
      9- interrupt-controller: identifies the node as an interrupt controller
     10- reg: physical base address of the controller and length of memory mapped
     11  region
     12- #interrupt-cells: specifies the number of cells needed to encode an interrupt
     13  source, should be 1.
     14- interrupts: specifies the interrupt line in the interrupt-parent controller