cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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ti,omap4-wugen-mpu (1111B)


      1TI OMAP4 Wake-up Generator
      2
      3All TI OMAP4/5 (and their derivatives) an interrupt controller that
      4routes interrupts to the GIC, and also serves as a wakeup source. It
      5is also referred to as "WUGEN-MPU", hence the name of the binding.
      6
      7Required properties:
      8
      9- compatible : should contain at least "ti,omap4-wugen-mpu" or
     10  "ti,omap5-wugen-mpu"
     11- reg : Specifies base physical address and size of the registers.
     12- interrupt-controller : Identifies the node as an interrupt controller.
     13- #interrupt-cells : Specifies the number of cells needed to encode an
     14  interrupt source. The value must be 3.
     15
     16Notes:
     17
     18- Because this HW ultimately routes interrupts to the GIC, the
     19  interrupt specifier must be that of the GIC.
     20- Only SPIs can use the WUGEN as an interrupt parent. SGIs and PPIs
     21  are explicitly forbidden.
     22
     23Example:
     24
     25       wakeupgen: interrupt-controller@48281000 {
     26               compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
     27               interrupt-controller;
     28               #interrupt-cells = <3>;
     29               reg = <0x48281000 0x1000>;
     30               interrupt-parent = <&gic>;
     31       };