cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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ti,sci-intr.yaml (3710B)

      1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/interrupt-controller/ti,sci-intr.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Texas Instruments K3 Interrupt Router
      8
      9maintainers:
     10  - Lokesh Vutla <lokeshvutla@ti.com>
     11
     12allOf:
     13  - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
     14
     15description: |
     16  The Interrupt Router (INTR) module provides a mechanism to mux M
     17  interrupt inputs to N interrupt outputs, where all M inputs are selectable
     18  to be driven per N output. An Interrupt Router can either handle edge
     19  triggered or level triggered interrupts and that is fixed in hardware.
     20
     21                                   Interrupt Router
     22                               +----------------------+
     23                               |  Inputs     Outputs  |
     24          +-------+            | +------+    +-----+  |
     25          | GPIO  |----------->| | irq0 |    |  0  |  |       Host IRQ
     26          +-------+            | +------+    +-----+  |      controller
     27                               |    .           .     |      +-------+
     28          +-------+            |    .           .     |----->|  IRQ  |
     29          | INTA  |----------->|    .           .     |      +-------+
     30          +-------+            |    .        +-----+  |
     31                               | +------+    |  N  |  |
     32                               | | irqM |    +-----+  |
     33                               | +------+             |
     34                               |                      |
     35                               +----------------------+
     36
     37  There is one register per output (MUXCNTL_N) that controls the selection.
     38  Configuration of these MUXCNTL_N registers is done by a system controller
     39  (like the Device Memory and Security Controller on K3 AM654 SoC). System
     40  controller will keep track of the used and unused registers within the Router.
     41  Driver should request the system controller to get the range of GIC IRQs
     42  assigned to the requesting hosts. It is the drivers responsibility to keep
     43  track of Host IRQs.
     44
     45  Communication between the host processor running an OS and the system
     46  controller happens through a protocol called TI System Control Interface
     47  (TISCI protocol).
     48
     49properties:
     50  compatible:
     51    const: ti,sci-intr
     52
     53  ti,intr-trigger-type:
     54    $ref: /schemas/types.yaml#/definitions/uint32
     55    enum: [1, 4]
     56    description: |
     57      Should be one of the following.
     58        1 = If intr supports edge triggered interrupts.
     59        4 = If intr supports level triggered interrupts.
     60
     61  interrupt-controller: true
     62
     63  '#interrupt-cells':
     64    const: 1
     65    description: |
     66      The 1st cell should contain interrupt router input hw number.
     67
     68  ti,interrupt-ranges:
     69    $ref: /schemas/types.yaml#/definitions/uint32-matrix
     70    description: |
     71      Interrupt ranges that converts the INTR output hw irq numbers
     72      to parents's input interrupt numbers.
     73    items:
     74      items:
     75        - description: |
     76            "output_irq" specifies the base for intr output irq
     77        - description: |
     78            "parent's input irq" specifies the base for parent irq
     79        - description: |
     80            "limit" specifies the limit for translation
     81
     82required:
     83  - compatible
     84  - ti,intr-trigger-type
     85  - interrupt-controller
     86  - '#interrupt-cells'
     87  - ti,sci
     88  - ti,sci-dev-id
     89  - ti,interrupt-ranges
     90
     91unevaluatedProperties: false
     92
     93examples:
     94  - |
     95    main_gpio_intr: interrupt-controller0 {
     96        compatible = "ti,sci-intr";
     97        ti,intr-trigger-type = <1>;
     98        interrupt-controller;
     99        interrupt-parent = <&gic500>;
    100        #interrupt-cells = <1>;
    101        ti,sci = <&dmsc>;
    102        ti,sci-dev-id = <131>;
    103        ti,interrupt-ranges = <0 360 32>;
    104    };