cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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allwinner,sun50i-h6-iommu.yaml (1257B)

      1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/iommu/allwinner,sun50i-h6-iommu.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Allwinner H6 IOMMU Device Tree Bindings
      8
      9maintainers:
     10  - Chen-Yu Tsai <wens@csie.org>
     11  - Maxime Ripard <mripard@kernel.org>
     12
     13properties:
     14  "#iommu-cells":
     15    const: 1
     16    description:
     17      The content of the cell is the master ID.
     18
     19  compatible:
     20    const: allwinner,sun50i-h6-iommu
     21
     22  reg:
     23    maxItems: 1
     24
     25  interrupts:
     26    maxItems: 1
     27
     28  clocks:
     29    maxItems: 1
     30
     31  resets:
     32    maxItems: 1
     33
     34required:
     35  - "#iommu-cells"
     36  - compatible
     37  - reg
     38  - interrupts
     39  - clocks
     40  - resets
     41
     42additionalProperties: false
     43
     44examples:
     45  - |
     46      #include <dt-bindings/interrupt-controller/arm-gic.h>
     47      #include <dt-bindings/interrupt-controller/irq.h>
     48
     49      #include <dt-bindings/clock/sun50i-h6-ccu.h>
     50      #include <dt-bindings/reset/sun50i-h6-ccu.h>
     51
     52      iommu: iommu@30f0000 {
     53          compatible = "allwinner,sun50i-h6-iommu";
     54          reg = <0x030f0000 0x10000>;
     55          interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
     56          clocks = <&ccu CLK_BUS_IOMMU>;
     57          resets = <&ccu RST_BUS_IOMMU>;
     58          #iommu-cells = <1>;
     59      };
     60
     61...