cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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apple,sart.yaml (1341B)

      1# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/iommu/apple,sart.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Apple SART DMA address filter
      8
      9maintainers:
     10  - Sven Peter <sven@svenpeter.dev>
     11
     12description:
     13  Apple SART is a simple address filter for DMA transactions. Regions of
     14  physical memory must be added to the SART's allow list before any
     15  DMA can target these. Unlike a proper IOMMU no remapping can be done and
     16  special support in the consumer driver is required since not all DMA
     17  transactions of a single device are subject to SART filtering.
     18
     19  SART1 has first been used since at least the A11 (iPhone 8 and iPhone X)
     20  and allows 36 bit of physical address space and filter entries with sizes
     21  up to 24 bit.
     22
     23  SART2, first seen in A14 and M1, allows 36 bit of physical address space
     24  and filter entry size up to 36 bit.
     25
     26  SART3, first seen in M1 Pro/Max, extends both the address space and filter
     27  entry size to 42 bit.
     28
     29properties:
     30  compatible:
     31    enum:
     32      - apple,t6000-sart
     33      - apple,t8103-sart
     34
     35  reg:
     36    maxItems: 1
     37
     38  power-domains:
     39    maxItems: 1
     40
     41required:
     42  - compatible
     43  - reg
     44
     45additionalProperties: false
     46
     47examples:
     48  - |
     49    iommu@7bc50000 {
     50      compatible = "apple,t8103-sart";
     51      reg = <0x7bc50000 0x4000>;
     52    };